Nexperia USA Inc. 74AUP2G157GT,115

Overview

74AUP2G157GT,115 from Nexperia is a low-power 2-input multiplexer in XSON8 package (SOT833-1), providing true and complement outputs (Y, Y) with active-low enable (E) and Schmitt-trigger inputs. It operates across 0.8 V to 3.6 V supply, delivers ≤1.4 μA ICC at −40 °C to +125 °C, supports IOFF for partial power-down, and is used in battery-powered sensor interface and voltage-level translation circuits.

For engineers reviewing the 74AUP2G157GT,115 datasheet, 74AUP2G157GT,115 pinout, 74AUP2G157GT,115 application, or 74AUP2G157GT,115 equivalent, key selection criteria include its dual-output logic architecture, ultra-low static current, IOFF-enabled isolation during power sequencing, and guaranteed operation down to 0.8 V for energy-constrained embedded systems.

Technical Context

The device implements a single 2:1 data selector with independent true (Y) and inverted (Y) outputs, controlled by a common select input (S) and active-low enable (E). Its Schmitt-trigger inputs ensure robust noise immunity across the full 0.8–3.6 V VCC range, enabling reliable operation with slow-rising signals in mixed-voltage domains.

IOFF circuitry disables both outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA, making it suitable for hot-swap and multi-rail power management. Propagation delays are specified down to 1.0 ns (CL = 5 pF, VCC = 3.0–3.6 V) and scale predictably with load capacitance and supply voltage.

Key Specifications

Pinout & Package

XSON8 plastic extremely thin small outline package (SOT833-1); no leads; 8 terminals; body dimensions 1.0 mm × 1.95 mm × 0.5 mm; thermal pad not present; pin 1 indicator located on lower-left corner below marking code "a2P".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input multiplexer applications.

Compared with SN74LVC2G157DCUR and 74LVC1G157GW,125, the 74AUP2G157GT,115 uniquely combines ultra-low ICC, IOFF, Schmitt inputs, and dual true/complement outputs - making it optimal for energy-sensitive, noise-prone, and multi-rail applications where signal integrity and power sequencing are critical.

Availability

74AUP2G157GT,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, battery-powered data acquisition systems, and voltage-level translation hubs requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for 74AUP2G157GT,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP (Advanced Ultra-low Power) product line targets ultra-low-power digital logic applications in portable, automotive, and industrial systems where nanowatt quiescent current and robust IOFF behavior are mandatory design requirements.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP2G157GT,115 allows input voltages up to 3.6 V regardless of VCC state, per datasheet Table 5 (VI input voltage limit: −0.5 V to +4.6 V). This enables safe "live insertion" into powered-backplane systems and protects against bus contention during power sequencing.

Does the device support hot-swap operation?

Yes - the IOFF circuitry actively disables outputs and limits power-off leakage to ±0.75 μA when VCC = 0 V, preventing backflow current through I/O pins. This meets hot-swap requirements for modular industrial controllers and telecom line cards without additional protection circuitry.

How does the Schmitt-trigger input improve system robustness?

Schmitt-trigger inputs provide hysteresis (typically 0.2–0.4 V depending on VCC), rejecting noise spikes and slow-rising signals that would cause multiple transitions on standard CMOS inputs. This eliminates false triggering in electrically noisy environments like motor drives or RF-dense enclosures.

Can Y and Y outputs drive complementary loads simultaneously?

Yes - Y and Y are fully buffered, independent outputs capable of sinking/sourcing ±20 mA each. They can drive complementary logic inputs (e.g., differential receivers) or parallel termination networks without interaction, provided total package power dissipation remains within 250 mW derating limits.