Nexperia USA Inc. 74AUP2G17GN,132
- Part No.:
- 74AUP2G17GN,132
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP2G17GN,132.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:99,656
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Product details
Overview
74AUP2G17GN,132 from Nexperia is a dual Schmitt-trigger buffer IC designed for noise-immune signal conditioning in ultra-low-power systems. It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 25 °C, features IOFF partial power-down protection, and supports −40 °C to +125 °C operation in the SOT1115 (XSON6) package. It is used in battery-powered sensor interfaces and I²C bus level-shifting circuits.
For engineers reviewing the 74AUP2G17GN,132 datasheet, 74AUP2G17GN,132 pinout, 74AUP2G17GN,132 application, or 74AUP2G17GN,132 equivalent, this device is selected for its sub-1-μA static current, rail-to-rail input tolerance up to 3.6 V, hysteresis-controlled noise rejection, and compatibility with mixed-voltage logic domains in portable and industrial edge nodes.
Technical Context
The 74AUP2G17GN,132 implements two independent CMOS Schmitt-trigger buffers with asymmetric hysteresis (VH = 0.79–1.31 V at VCC = 3.0 V), enabling reliable waveform shaping of slow or noisy digital signals. Its IOFF circuit actively disables outputs during VCC = 0 V, preventing backflow current in partial power-down systems.
It complies with JEDEC standards JESD8-12 through JESD8C across five VCC ranges and achieves HBM ESD robustness >5000 V and CDM >1000 V. Input thresholds (VT+ and VT−) are tightly specified across temperature and voltage, ensuring consistent switching behavior in thermally varying environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - Enables direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max ICC (Static) | 0.9 μA at −40 °C to +125 °C - Ensures negligible battery drain in always-on sensor nodes and wake-up circuits. |
| Hysteresis Voltage (VH) | 0.79–1.31 V at VCC = 3.0 V - Provides ≥400 mV noise margin against EMI in motor control feedback or industrial I/O lines. |
| Propagation Delay | 1.5–4.0 ns at VCC = 3.0 V, CL = 5 pF - Supports clean signal routing in high-speed low-power microcontroller GPIO expansion. |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - Prevents cross-talk and power loss when one subsystem powers down while others remain active. |
| Input Overvoltage Tolerance | Up to 3.6 V regardless of VCC - Allows safe interfacing with 3.3 V signals even when VCC = 1.2 V (e.g., I²C pull-up to higher rail). |
| Operating Temperature | −40 °C to +125 °C - Qualified for under-hood automotive modules and industrial PLC I/O cards. |
Pinout & Package
XSON6 package (SOT1115): extremely thin small outline, no leads, 6-terminal surface-mount with 0.9 × 1.0 × 0.35 mm body and bottom-side thermal pad (non-electrical). Pin 1 index located on lower-left corner below marking code "pV".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1A | First Schmitt-trigger input - Accepts slow-rising signals (e.g., mechanical switch bounce, analog comparator output) with hysteresis filtering. |
| 2 | GND | Dedicated ground reference - Must be connected to system ground plane to ensure stable threshold referencing and noise immunity. |
| 3 | 2A | Second Schmitt-trigger input - Independent channel enables dual-signal conditioning (e.g., CLK and DATA lines in SPI slave interface). |
| 4 | 2Y | Second buffered output - Drives capacitive loads up to 30 pF with <4.8 ns delay at 3.0 V, supporting fan-out to multiple downstream gates. |
| 5 | VCC | Single supply rail - Powers both channels; IOFF remains active even if VCC drops to 0 V, isolating output from backfeed. |
| 6 | 1Y | First buffered output - Delivers rail-aligned HIGH/LOW levels with VOH ≥2.30 V and VOL ≤0.50 V at 3.0 V/4 mA load. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC ≤ 0.9 μA max over full temperature range - Extends battery life in coin-cell-powered IoT endpoints beyond 10 years. |
| IOFF partial power-down | Output disabled with VCC = 0 V and VI/VO = 0–3.6 V - Eliminates need for external isolation switches in multi-rail power architectures. |
| Wide-input hysteresis | VH = 0.79–1.31 V at VCC = 3.0 V - Rejects >300 mV of common-mode noise on long PCB traces or unshielded cables. |
| Rail-tolerant inputs | VI rated to 3.6 V independent of VCC - Enables direct connection to 3.3 V I²C buses while operating from 1.8 V core supply. |
| High ESD robustness | HBM >5000 V, CDM >1000 V - Survives handling and board-level ESD events without shielding or external TVS diodes. |
Applications
| Industrial Sensor Interface | Low-Power Microcontroller GPIO Expansion |
|---|---|
|
Use Scenario: Conditioning slow, noisy output from MEMS accelerometers or thermistor-based analog comparators in factory-floor monitoring nodes. IC Role / Device Role / Timing Role: Dual Schmitt-trigger buffer cleans asynchronous switch closures and analog comparator edges before MCU interrupt input or ADC trigger. Use Value: Eliminates software debouncing overhead and reduces false triggers by >99.7% under 200 mV RMS conducted noise. |
Use Scenario: Level-shifting and signal integrity enhancement for GPIO expansion on 1.2 V or 1.8 V MCUs interfacing with 3.3 V peripherals (e.g., SD card, UART transceivers). IC Role / Device Role / Timing Role: Bidirectional buffer with rail-tolerant inputs ensures reliable communication without external level translators. Use Value: Reduces BOM count by one IC per signal pair and cuts PCB area by 35% versus discrete MOSFET-based solutions. |
| I²C Bus Signal Conditioning | Automotive Body Control Module I/O |
|
Use Scenario: Strengthening SDA/SCL lines in multi-drop I²C networks with long trace lengths (>15 cm) and multiple slaves in smart lighting or HVAC controllers. IC Role / Device Role / Timing Role: Acts as repeater buffer with hysteresis to restore rise/fall times and suppress ringing-induced glitches. Use Value: Enables reliable 400 kHz I²C operation at 20 cm trace length where unbuffered lines fail above 100 kHz. |
Use Scenario: Debouncing and ESD protection for door lock actuator feedback, seat position sensors, and ambient light detector inputs in BCMs. IC Role / Device Role / Timing Role: Input conditioner providing noise immunity and IOFF isolation during sleep mode (VCC off but sensor lines live). Use Value: Meets ISO 10605 ESD requirements without additional protection components and maintains zero current draw in vehicle sleep state. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual Schmitt-trigger buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G17DBVR | Wider VCC range (1.65–5.5 V); higher ICC (max 10 μA); no IOFF; larger SOT-23-6 package (2.9 × 1.6 mm). | Not suitable for sub-1-V operation or partial power-down systems; requires external isolation for VCC-off scenarios. | Select when interfacing with 5 V legacy peripherals and board space is not constrained. |
| 74LVC2G17GW,125 | Same AUP family architecture but in TSSOP6 (SOT363-2); 1.25 mm body width; slightly higher thermal resistance (83 °C/W vs 71 °C/W for SOT1115). | Less optimal for ultra-thin wearable designs; same electrical specs but less efficient heat dissipation at high ambient temperatures. | Select when hand-soldering or rework is required - TSSOP6 offers better solder joint visibility than XSON6. |
Compared with SN74LVC2G17DBVR and 74LVC2G17GW,125, the 74AUP2G17GN,132 uniquely combines sub-1-μA static current, 0.8 V minimum VCC, and guaranteed IOFF - making it the only choice for energy-harvesting sensors and automotive sleep-mode I/O where leakage must stay below 1 μA.
Availability
74AUP2G17GN,132 is available at Aetrix Electronics and suitable for battery-powered sensor nodes, industrial I/O conditioners, and automotive body control modules requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP2G17GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.
The 74AUP (Advanced Ultra-low Power) product line targets ultra-low-power digital signal conditioning in portable, industrial, and automotive applications where nanowatt standby current and robust noise immunity are mandatory design requirements.
FAQ
Does 74AUP2G17GN,132 support true bidirectional signal flow?
No - it is a unidirectional buffer: inputs (1A, 2A) accept signals and outputs (1Y, 2Y) drive loads. Each channel operates independently with Schmitt-trigger input and push-pull CMOS output. It does not implement bus transceiver logic or direction control pins.
Can 74AUP2G17GN,132 be used with VCC = 0 V while inputs remain at 3.3 V?
Yes - the IOFF circuitry guarantees that outputs are high-impedance and leakage remains ≤±0.75 μA when VCC = 0 V, even with VI or VO held at 0–3.6 V. This meets JESD78 Class II latch-up immunity and prevents backfeed into powered-down subsystems.
What is the minimum load capacitance for guaranteed timing performance?
The propagation delay specifications (e.g., 1.5–4.0 ns at VCC = 3.0 V) are validated at CL = 5 pF, including probe and jig capacitance. Performance degrades linearly with increasing CL - at 30 pF, tpd increases to 3.1–7.5 ns. No minimum CL is required; operation is valid down to 0 pF.
How does hysteresis vary with supply voltage?
Hysteresis voltage (VH = VT+ − VT−) scales with VCC: 0.07–0.50 V at 0.8 V, rising to 0.79–1.31 V at 3.0 V. Thresholds VT+ and VT− track VCC proportionally (e.g., VT+ ≈ 0.63×VCC at 3.0 V), maintaining consistent noise margin percentage across the full 0.8–3.6 V range.
74AUP2G17GN,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- Schmitt Trigger
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON (0.9x1)
74AUP2G17GN,132 FAQ
1.How can I place an order for 74AUP2G17GN,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G17GN,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G17GN,132 reliable?
The price and inventory of 74AUP2G17GN,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G17GN,132 is usually 5 days.
3.What payment methods are accepted for 74AUP2G17GN,132?
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4.How is shipping managed for 74AUP2G17GN,132?
74AUP2G17GN,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G17GN,132 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G17GN,132?
For technical support, including 74AUP2G17GN,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G17GN,132 requirements.
6.How does Aetrix verify that 74AUP2G17GN,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G17GN,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G17GN,132 meets industry standards.
7.What is the process for return or replacement of 74AUP2G17GN,132?
All 74AUP2G17GN,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G17GN,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G17GN,132 part is unused and in its original packaging.
Return procedure for 74AUP2G17GN,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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