Nexperia USA Inc. 74AUP2G17GW,125

Overview

74AUP2G17GW,125 from Nexperia is a dual Schmitt-trigger buffer IC designed for noise-immune signal conditioning in ultra-low-power systems. It operates across 0.8 V to 3.6 V supply, delivers <0.9 μA max ICC at 25 °C, supports partial power-down via IOFF (≤±0.75 μA off-state leakage), and features hysteresis (VH = 0.79–1.31 V at VCC = 3.0 V) for reliable edge detection in slow-rising input environments - used in battery-powered sensor interfaces and I²C bus level-shifting.

For engineers reviewing the 74AUP2G17GW,125 datasheet, 74AUP2G17GW,125 pinout, 74AUP2G17GW,125 application, or 74AUP2G17GW,125 equivalent, this device is selected for its sub-1 μA static current, overvoltage-tolerant inputs (up to 3.6 V), low-noise switching (<10% VCC overshoot/undershoot), and guaranteed operation from –40 °C to +125 °C in TSSOP6 packaging.

Technical Context

The 74AUP2G17GW,125 implements two independent Schmitt-trigger buffers with asymmetric hysteresis thresholds (VT+ = 1.88–2.32 V, VT− = 0.88–1.24 V at VCC = 3.0 V), enabling robust noise rejection on digital inputs subject to slow slew rates or EMI. Its IOFF circuit actively disables outputs during power-down, preventing backflow current when VCC = 0 V.

It complies with JEDEC standards JESD8-12 through JESD8C across five voltage bands and meets HBM ESD rating >5000 V and CDM >1000 V. Propagation delay ranges from 1.5 ns (VCC = 3.0–3.6 V, CL = 5 pF) to 7.5 ns (VCC = 3.0–3.6 V, CL = 30 pF), with CPD = 4.0 pF at VCC = 3.0–3.6 V.

Key Specifications

Pinout & Package

TSSOP6 package (SOT363-2): plastic thin shrink small outline, 6-lead, 1.25 mm body width, 0.65 mm lead pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual Schmitt-trigger buffer applications.

Compared with SN74LVC2G17DBVR and 74LVC2G17GM,132, the 74AUP2G17GW,125 uniquely supports 0.8 V operation and IOFF-based power gating - critical for energy harvesting and fail-safe subsystem isolation where supply sequencing matters.

Availability

74AUP2G17GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, battery-powered remote monitoring, and automotive body control modules requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP2G17GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading semiconductor manufacturer specializing in high-performance, energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-constrained and thermally sensitive applications, delivering sub-microamp static current and robust noise immunity without sacrificing speed or voltage flexibility.

FAQ

Can 74AUP2G17GW,125 operate with VCC = 0.8 V while accepting 3.3 V inputs?

Yes. Its inputs are overvoltage tolerant up to 3.6 V regardless of VCC level, and it functions correctly at VCC = 0.8 V with guaranteed VOH/VOL performance per Table 7. This enables direct interfacing between legacy 3.3 V peripherals and next-gen sub-1 V MCUs without level shifters.

What happens to outputs during power-down (VCC = 0 V)?

When VCC = 0 V, the IOFF circuitry actively disables both outputs (1Y and 2Y), limiting leakage to ±0.75 μA maximum. This prevents back-current flow into powered sections of the system, protecting downstream logic and enabling safe hot-swap of subsystems.

How does hysteresis improve noise immunity in real-world circuits?

Hysteresis creates separate input thresholds for rising (VT+) and falling (VT−) edges - e.g., 1.88 V and 0.88 V at VCC = 3.0 V - resulting in 1.0 V noise margin. This prevents multiple toggles when input signals hover near the switching point due to EMI, crosstalk, or slow RC decay, eliminating need for external RC filters or firmware debouncing.

Is thermal derating required for continuous operation at +125 °C?

Yes. For the TSSOP6 (SOT363-2) package, total power dissipation derates linearly at 3.7 mW/K above +83 °C. At +125 °C, Ptot is reduced to ~250 mW × (1 − (125−83)×3.7/1000) ≈ 234 mW - well above the device's typical 10 μW dynamic dissipation, so no thermal design action is needed for standard use cases.