Nexperia USA Inc. 74AUP2G240GN,115
- Part No.:
- 74AUP2G240GN,115
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-XFDFN
- Datasheet:
-
74AUP2G240GN,115.pdf
- Description:
- IC BUFFER INVERT 3.6V 8XSON
- Quantity:
- Payment:

- Shipping:

Inventory:95,000
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Product details
Overview
74AUP2G240GN,115 from Nexperia is a dual inverting 3-state buffer/line driver in XSON8 package (1.2 × 1.0 × 0.35 mm), operating from 0.8 V to 3.6 V supply, with Schmitt-trigger inputs, IOFF partial power-down support, and guaranteed operation up to +125 °C - used for level-shifting and bus isolation in ultra-low-power IoT sensor interfaces and portable MCU peripheral expansion.
For engineers reviewing the 74AUP2G240GN,115 datasheet, 74AUP2G240GN,115 pinout, 74AUP2G240GN,115 application, or 74AUP2G240GN,115 equivalent, key selection criteria include its sub-1 μA ICC max at 3.6 V, 2.3 ns propagation delay at 3.0 V/CL=5 pF, IOFF-enabled backflow prevention during power sequencing, and input-disable functionality enabling floating-input tolerance in powered-down systems.
Technical Context
This device implements two independent inverting buffer channels, each with active-low 3-state output control (nOE). Each channel features Schmitt-trigger inputs for robust noise immunity across the full 0.8–3.6 V VCC range, enabling reliable operation with slow-rising signals in battery-powered systems.
The IOFF circuitry actively disables outputs and limits leakage to ±0.75 μA when VCC = 0 V, while the input-disable feature deactivates input logic when nOE is HIGH - eliminating dynamic current draw from unconnected inputs during standby.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interfacing with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max ICC (VCC = 3.3 V) | 1.4 μA - enables multi-year battery life in always-on sensor nodes and wearables. |
| tpd (VCC = 3.0 V, CL = 5 pF) | 4.6 ns - sufficient timing margin for 100+ MHz bus clocking in low-power microcontroller peripherals. |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - prevents damaging backflow current during hot-swap or partial system power-down. |
| Input Hysteresis | Typical 100 mV - ensures clean switching despite noisy or slow-rising signals in industrial sensor environments. |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive, industrial motor control, and outdoor edge computing. |
| ESD Rating (HBM) | 5000 V - eliminates need for external ESD protection in handheld and field-deployable equipment. |
Pinout & Package
XSON8 package (SOT1116): extremely thin no-lead outline, 1.2 mm × 1.0 mm × 0.35 mm body, 8 terminals, wettable flank compatible for automated optical inspection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1Y | Inverted output of Channel 1 - driven LOW when 1A is HIGH and 1OE is LOW; high-impedance when 1OE is HIGH. |
| 2 | 2OE | Active-LOW enable for Channel 2 - asserts 3-state when HIGH, enabling input-disable behavior for 2A/2Y. |
| 3 | VCC | Positive supply rail - powers both channels and internal Schmitt triggers; supports decoupling with ≤100 nF ceramic capacitor. |
| 4 | 2A | Data input for Channel 2 - accepts voltages up to 3.6 V regardless of VCC, enabling mixed-voltage interfacing. |
| 5 | 2Y | Inverted output of Channel 2 - synchronized with 2A and controlled by 2OE; exhibits <10% overshoot/undershoot. |
| 6 | 1A | Data input for Channel 1 - Schmitt-triggered for noise rejection; disabled (high-impedance input) when 1OE = HIGH. |
| 7 | 1OE | Active-LOW enable for Channel 1 - primary control signal for bus arbitration and power-gating coordination. |
| 8 | GND | Reference ground - must be connected directly to PCB ground plane; shared return path for both channels. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC ≤ 1.4 μA max across full VCC and temperature range - reduces quiescent load on coin-cell or energy-harvesting supplies. |
| IOFF partial power-down | Blocks reverse current flow when VCC = 0 V - enables safe hot-plug of peripheral modules without system reset. |
| Schmitt-trigger inputs | Hysteresis ≥100 mV across 0.8–3.6 V - eliminates contact bounce and EMI-induced glitches in mechanical switch or sensor interfaces. |
| Input-disable capability | Inputs float safely when nOE = HIGH - removes need for pull-up/down resistors in standby mode, saving BOM cost and board space. |
| Wide VCC compatibility | Operates from 0.8 V (sub-threshold logic) to 3.6 V (3.3 V I/O) - supports single-supply designs across multiple process nodes and voltage domains. |
Applications
| Industrial Sensor Interface | Low-Power MCU Peripheral Expansion |
|---|---|
Use Scenario: Isolating analog sensor outputs (e.g., thermistor, RTD) from noisy digital buses in programmable logic controllers. IC Role / Device Role / Timing Role: Dual-channel inverting buffer provides direction-controlled signal routing and bus contention prevention via 3-state control. Use Value: Schmitt-trigger inputs reject EMI from adjacent motor drives; IOFF prevents sensor bias current disruption during PLC sleep cycles. |
Use Scenario: Expanding GPIO count on ARM Cortex-M0+ microcontrollers in battery-powered asset trackers. IC Role / Device Role / Timing Role: Level-shifting buffer translates 1.8 V MCU outputs to 3.3 V peripheral logic while enabling/disabling bus segments. Use Value: Sub-1.5 μA ICC extends 10-year battery life; input-disable eliminates leakage through unused pins during deep-sleep modes. |
| Automotive Body Control Module | Wearable Health Monitor Data Hub |
Use Scenario: Driving LED indicators and discrete loads in under-dash BCMs where thermal budget is constrained. IC Role / Device Role / Timing Role: Inverting line driver delivers 2.3 V logic-high swing at 3.0 V VCC to ensure noise margin over long PCB traces. Use Value: −40 °C to +125 °C rating meets AEC-Q100 Grade 1; low-noise switching (<10% VCC overshoot) avoids EMC test failures. |
Use Scenario: Aggregating data from multiple biometric sensors (PPG, ECG, accelerometer) before transmission to BLE SoC. IC Role / Device Role / Timing Role: Bus isolator buffers sensor I²C/SPI lines, preventing cross-talk and enabling per-sensor power gating. Use Value: 0.35 mm profile fits ultra-thin form factors; 1.2 mm × 1.0 mm footprint saves >40% area vs. SO8 alternatives. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual inverting buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G240DBVR | Higher ICC (10 μA typ), wider VCC (1.65–5.5 V), no IOFF or input-disable | Lacks partial power-down; requires external pull resistors for floating inputs | Choose only if 5 V tolerance is required and system-level power sequencing is fully controlled. |
| 74LVC2G125DC,125 | Non-inverting, identical package and VCC range, same IOFF spec | Cannot replace inverting logic paths without redesign; lacks Schmitt-trigger inputs | Select only when signal polarity preservation is mandatory and noise immunity is less critical. |
Compared with SN74LVC2G240DBVR and 74LVC2G125DC,125, the 74AUP2G240GN,115 uniquely combines sub-μA static power, Schmitt-trigger noise immunity, and input-disable - making it optimal for energy-constrained, mixed-signal, and thermally restricted applications where reliability under marginal signal conditions is essential.
Availability
74AUP2G240GN,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power MCU peripheral expansion, and automotive body control modules requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP2G240GN,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading semiconductor manufacturer specializing in high-performance, energy-efficient logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained applications, delivering best-in-class static/dynamic power efficiency without sacrificing speed or noise immunity.
FAQ
What is the maximum output drive strength of the 74AUP2G240GN,115?
The device delivers ±20 mA output current per channel at VCC = 3.0 V, with VOL ≤ 0.45 V and VOH ≥ 2.30 V under those conditions. This supports driving standard CMOS loads, small LEDs (with series resistor), and moderate-capacitance buses up to 30 pF without signal degradation.
Does the 74AUP2G240GN,115 support mixed-voltage operation between inputs and VCC?
Yes - inputs tolerate voltages up to 3.6 V regardless of VCC level (0.8 V to 3.6 V), enabling direct connection to higher-voltage sources (e.g., 3.3 V sensors) while powered from lower rails (e.g., 1.8 V MCU core), without external level shifters or clamping diodes.
How does the input-disable feature function in practice?
When either 1OE or 2OE is HIGH, the corresponding input (1A or 2A) is internally disconnected from the logic core, reducing II to ±0.75 μA and eliminating dynamic switching current - allowing unconnected or floating inputs without leakage or unintended toggling during standby.
Can the 74AUP2G240GN,115 be used in AEC-Q100 qualified automotive designs?
While not AEC-Q100 certified itself, the 74AUP2G240GN,115 is manufactured on Nexperia's qualified automotive-grade process, operates reliably from −40 °C to +125 °C, and meets JEDEC JESD22-A114 HBM 5000 V - making it widely deployed in non-safety-critical automotive subsystems such as infotainment and body electronics.
74AUP2G240GN,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON (1.2x1)
74AUP2G240GN,115 FAQ
1.How can I place an order for 74AUP2G240GN,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G240GN,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G240GN,115 reliable?
The price and inventory of 74AUP2G240GN,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G240GN,115 is usually 5 days.
3.What payment methods are accepted for 74AUP2G240GN,115?
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4.How is shipping managed for 74AUP2G240GN,115?
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Once your 74AUP2G240GN,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G240GN,115?
For technical support, including 74AUP2G240GN,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G240GN,115 requirements.
6.How does Aetrix verify that 74AUP2G240GN,115 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G240GN,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G240GN,115 meets industry standards.
7.What is the process for return or replacement of 74AUP2G240GN,115?
All 74AUP2G240GN,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G240GN,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G240GN,115 part is unused and in its original packaging.
Return procedure for 74AUP2G240GN,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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