Nexperia USA Inc. 74AUP2G240GS,115

Overview

74AUP2G240GS,115 from Nexperia is a low-power dual inverting buffer/line driver with 3-state outputs, designed for voltage-level translation and bus isolation in ultra-low-power systems operating from 0.8 V to 3.6 V. It features Schmitt-trigger inputs for noise immunity, IOFF circuitry for partial power-down protection, and input-disable functionality when output enable (nOE) is HIGH. Used in portable sensor interfaces and battery-powered microcontroller I/O expansion.

For engineers reviewing the 74AUP2G240GS,115 datasheet, 74AUP2G240GS,115 pinout, 74AUP2G240GS,115 application, or 74AUP2G240GS,115 equivalent, key selection criteria include its 0.9 μA max ICC at 3.6 V, 1.35 × 1.0 × 0.35 mm XSON8 package, -40 °C to +125 °C operation, IOFF-enabled power-down behavior, and dual-channel inverting 3-state logic function.

Technical Context

This device implements two independent inverting buffer stages, each with active-low 3-state control via dedicated nOE inputs. Each channel accepts input voltages up to 3.6 V regardless of VCC, enabling level-shifting between disparate supply domains. Schmitt-trigger inputs ensure robust operation with slow-rising signals across the full 0.8–3.6 V VCC range.

The IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V, while input-disable prevents floating-input leakage when nOE is HIGH. Propagation delay is as low as 1.4 ns (VCC = 3.6 V, CL = 5 pF), with enable/disable times under 5.3 ns, supporting high-speed bus arbitration in compact embedded systems.

Key Specifications

Pinout & Package

XSON8 package (SOT1203): extremely thin small outline, no leads, 8-terminal, body dimensions 1.35 × 1.0 × 0.35 mm, thermal pad optional, pin 1 marked by lower-left corner dot below marking code "p2".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual inverting buffer/line driver applications.

Compared with SN74LVC2G240DBVR, the 74AUP2G240GS,115 delivers 11× lower static current and IOFF protection critical for battery longevity; versus 74AUP2G125GS,115, it provides inverting logic essential for active-low enable signaling and bus polarity alignment.

Availability

74AUP2G240GS,115 is available at Aetrix Electronics and suitable for industrial sensor hubs, portable medical monitors, automotive body control modules, and smart home edge nodes requiring stable component supply across extended temperature ranges and ultra-low-power operation.

Supply support for 74AUP2G240GS,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained applications demanding sub-microamp quiescent current, wide VCC flexibility, and robust IO protection - optimized for portable, IoT, and automotive edge devices.

FAQ

What is the maximum load capacitance supported at 3.6 V supply?

The device is characterized up to 30 pF load capacitance at VCC = 3.6 V, with propagation delay increasing from 1.4 ns (CL = 5 pF) to 2.6 ns (CL = 30 pF). Output drive strength remains stable across this range, and no derating is required for CL ≤ 30 pF per the datasheet's dynamic characteristics tables.

Can 74AUP2G240GS,115 interface a 1.2 V MCU with a 3.3 V peripheral?

Yes - inputs accept voltages up to 3.6 V regardless of VCC, so the 3.3 V peripheral outputs can safely drive the 74AUP2G240GS,115 inputs while VCC = 1.2 V. The buffered outputs will swing between 0 V and 1.2 V, requiring an additional level shifter only if the peripheral needs 3.3 V logic levels back.

Does the XSON8 package (SOT1203) require thermal vias under the die pad?

No thermal pad is present in the SOT1203 package - unlike some XSON variants, this variant has no exposed thermal pad. The 1.35 × 1.0 mm body relies on solder joint conduction and PCB copper area for thermal dissipation; recommended layout uses ≥2 mm² of 1-oz copper connected to GND on adjacent layers.

How does input-disable behave when nOE is HIGH and VCC is unpowered?

When nOE is HIGH and VCC = 0 V, the input-disable feature remains active: internal input buffers are turned off, limiting II to ±0.75 μA maximum. This prevents leakage-induced false triggering and protects upstream drivers from back-biasing, satisfying IEC 61000-4-2 system-level ESD robustness requirements.