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Nexperia USA Inc. 74AUP2G32DC,125
- Part No.:
- 74AUP2G32DC,125
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 8-VFSOP (0.091", 2.30mm Width)
- Datasheet:
-
74AUP2G32DC,125.pdf
- Description:
- IC GATE OR 2CH 2-INP 8VSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:11,137
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Product details
Overview
74AUP2G32DC,125 from Nexperia is a low-power dual 2-input OR gate in VSSOP8 (SOT765-1) package, operating from 0.8 V to 3.6 V supply. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and guaranteed operation from –40 °C to +125 °C. Used in battery-powered sensor interfaces and level-shifting logic blocks where ultra-low static current (<0.9 μA max) and rail-to-rail input tolerance are critical.
For engineers reviewing the 74AUP2G32DC,125 datasheet, 74AUP2G32DC,125 pinout, 74AUP2G32DC,125 application, or 74AUP2G32DC,125 equivalent, this device serves as a drop-in logic building block in space-constrained, wide-VCC industrial control modules, portable instrumentation, and automotive body electronics requiring robust input rise/fall time tolerance and zero backflow current during partial power-down.
Technical Context
The 74AUP2G32DC,125 implements two independent OR gates with Schmitt-trigger inputs-each accepting overvoltage-tolerant signals up to 3.6 V regardless of VCC level. Its IOFF circuit actively disables outputs when VCC = 0 V, blocking destructive backflow current during hot-insertion or mixed-supply sequencing.
Propagation delay ranges from 0.9 ns (VCC = 3.0 V, CL = 5 pF) to 23.8 ns (VCC = 0.8 V, CL = 15 pF), with dynamic power dissipation governed by CPD = 3.7 pF at 3.6 V. Input leakage remains ≤±0.75 μA across full temperature range, enabling reliable operation in high-impedance signal routing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 0.8 V to 3.6 V - supports single-cell Li-ion, 1.2 V NiMH, 1.8 V/2.5 V/3.3 V logic domains without level shifters |
| Max ICC | 0.9 μA at 25 °C - enables multi-year battery life in always-on wake-up logic paths |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents cross-conduction in partially powered subsystems |
| tpd (VCC = 3.3 V) | 1.2 ns (CL = 5 pF) - meets timing closure in sub-500 MHz clock domain fanout |
| Input Voltage Range | –0.5 V to +4.6 V - withstands transient overshoot beyond VCC without clamping diode conduction |
| Operating Temp | –40 °C to +125 °C - qualified for under-hood automotive and industrial motor drive control |
| ESD Rating | HBM >5000 V, CDM >1000 V - survives handling and board-level ESD events without screening |
Pinout & Package
VSSOP8 plastic very thin shrink small outline package (SOT765-1), 8 leads, body width 2.3 mm, 0.5 mm pitch, exposed pad not present.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1A | First OR gate input A - accepts Schmitt-triggered logic signal with hysteresis ≥0.1×VCC |
| 2 | 1B | First OR gate input B - fully compatible with 1A; both inputs tolerant to 3.6 V regardless of VCC |
| 3 | 1Y | First OR gate output Y - drives CMOS loads up to ±4 mA at VCC = 3.0 V |
| 4 | GND | Ground reference - must be connected before VCC to avoid latch-up risk |
| 5 | 2A | Second OR gate input A - electrically isolated from first gate; identical AC/DC specs |
| 6 | 2B | Second OR gate input B - supports independent logic functions on same die |
| 7 | 2Y | Second OR gate output Y - provides separate output path with no internal coupling to 1Y |
| 8 | VCC | Supply voltage - powers both gates; IOFF activates automatically when VCC = 0 V |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Enables clean logic transitions on slow-rising signals (e.g., thermistor RC networks or mechanical switch debouncing) without external hysteresis components |
| IOFF partial power-down | Prevents backflow current when VCC is removed while inputs remain active - essential for hot-swap I/O expansion cards |
| Wide VCC range (0.8–3.6 V) | Eliminates need for multiple logic families across mixed-voltage systems - one part covers 1.2 V, 1.8 V, 2.5 V, and 3.3 V domains |
| Overvoltage-tolerant inputs | Accepts 3.6 V inputs even at VCC = 0.8 V - simplifies interface to higher-voltage sensors or legacy peripherals |
| Low-noise switching | Overshoot/undershoot <10 % of VCC - reduces EMI in sensitive analog-adjacent PCB layouts |
Applications
| Industrial Sensor Interface | Automotive Body Control |
|---|---|
|
Use Scenario: Combining fault signals from multiple temperature, pressure, and door-switch sensors into a single alert line feeding a microcontroller interrupt pin. IC Role / Device Role / Timing Role: Dual OR gate aggregates asynchronous digital status bits; Schmitt inputs reject noise from long cable runs. Use Value: Reduces MCU GPIO count by 2× while maintaining deterministic response to any sensor fault - no software polling required. |
Use Scenario: Enabling headlight power stage only when both ignition ON and light switch is activated, with fail-safe override if either signal fails high. IC Role / Device Role / Timing Role: Logic-level OR gate performs real-time hardware interlock; IOFF prevents backfeed during battery disconnect. Use Value: Meets ISO 16750-2 transient immunity requirements without external protection diodes or pull resistors. |
| Portable Medical Device | IoT Edge Node |
|
Use Scenario: Wake-up logic that triggers system-on-chip (SoC) from deep sleep when either motion sensor or button press occurs. IC Role / Device Role / Timing Role: Ultra-low-ICC OR gate acts as always-on combiner; operates down to 0.8 V during brownout conditions. Use Value: Extends battery runtime by >12 months in standby mode versus standard 74LVC logic (ICC ≈ 2 μA typical). |
Use Scenario: Signal conditioning for LoRaWAN node transmitting environmental data - OR-ing PIR motion detection and periodic timer pulses to initiate transmission. IC Role / Device Role / Timing Role: Low-capacitance (CI = 0.6 pF) gate minimizes loading on high-impedance timer output; CPD = 3.7 pF limits dynamic power. Use Value: Enables 10+ year coin-cell operation by reducing wake-up path power by 65 % vs. discrete MOSFET-based OR solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 2-input OR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC2G32GM,132 | Higher ICC (max 4 μA), no Schmitt inputs, VCC min = 1.65 V | Unsuitable for sub-1.65 V battery operation or noisy sensor inputs | Select only if VCC ≥ 1.8 V and input edges are fast/rail-to-rail |
| SN74AUP2G32DCKR | Identical electrical specs; same VSSOP8 package but TI marking and tape/reel packaging | No functional difference; pinout and thermal performance match exactly | Use for second-source assurance with identical design-in qualification |
Compared with 74LVC2G32GM,132, the 74AUP2G32DC,125 delivers 4.4× lower static current and Schmitt noise rejection; versus SN74AUP2G32DCKR, it offers identical performance with Nexperia's extended -40 °C to +125 °C qualification and tighter IOFF leakage spec (±0.75 μA vs. ±1.0 μA).
Availability
74AUP2G32DC,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control units, portable medical devices, and IoT edge nodes requiring stable component supply across extended temperature and ultra-low power constraints.
Supply support for 74AUP2G32DC,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume applications.
The 74AUP (Advanced Ultra-low Power) family targets battery-powered and energy-sensitive systems where sub-1 μA static current, wide VCC operation, and robust IO behavior are mandatory design requirements.
FAQ
Does 74AUP2G32DC,125 support true bidirectional operation?
No. The 74AUP2G32DC,125 is a unidirectional logic gate with defined inputs (1A/1B/2A/2B) and outputs (1Y/2Y). It lacks bus-hold or direction-control circuitry. Inputs accept signals up to 3.6 V regardless of VCC, but outputs cannot source/sink current into input pins without violating absolute maximum ratings.
Can 74AUP2G32DC,125 drive a 50 pF load at 3.3 V?
Yes, but with increased propagation delay: tpd rises to ~7.7 ns (CL = 30 pF, VCC = 3.3 V) per Table 8. For CL = 50 pF, extrapolation suggests ~9.2 ns. Output drive strength remains sufficient (±4 mA), but ensure timing margins accommodate the added capacitive load.
What is the minimum recommended VCC for guaranteed operation at –40 °C?
0.8 V is the absolute minimum specified across –40 °C to +125 °C. At –40 °C and VCC = 0.8 V, VIH = 0.75 × VCC = 0.6 V and VOL ≤ 0.11 V (IO = 1.1 mA), ensuring noise margin >0.2 V. Operation below 0.8 V is not characterized or guaranteed.
Is the VSSOP8 package (SOT765-1) RoHS and REACH compliant?
Yes. Nexperia confirms the 74AUP2G32DC,125 in SOT765-1 packaging meets RoHS Directive 2011/65/EU and REACH Regulation (EC) No. 1907/2006, including SVHC candidate list compliance as of the August 2024 revision. Full material declarations are available via Nexperia's Product Change Notification portal.
74AUP2G32DC,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 8-VFSOP (0.091", 2.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- OR Gate
- Number of Circuits:
- 2
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 6.4ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-VSSOP
74AUP2G32DC,125 FAQ
1.How can I place an order for 74AUP2G32DC,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G32DC,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G32DC,125 reliable?
The price and inventory of 74AUP2G32DC,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G32DC,125 is usually 5 days.
3.What payment methods are accepted for 74AUP2G32DC,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G32DC,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP2G32DC,125?
74AUP2G32DC,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G32DC,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G32DC,125?
For technical support, including 74AUP2G32DC,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G32DC,125 requirements.
6.How does Aetrix verify that 74AUP2G32DC,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G32DC,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G32DC,125 meets industry standards.
7.What is the process for return or replacement of 74AUP2G32DC,125?
All 74AUP2G32DC,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G32DC,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G32DC,125 part is unused and in its original packaging.
Return procedure for 74AUP2G32DC,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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