Nexperia USA Inc. 74AUP2G32GM,125

Overview

74AUP2G32GM,125 from Nexperia is a low-power dual 2-input OR gate logic IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ≤0.9 μA max ICC at 25 °C, and supporting partial power-down via IOFF circuitry. It is used in battery-powered sensor interface signal conditioning where noise immunity and ultra-low static power are critical.

For engineers reviewing the 74AUP2G32GM,125 datasheet, 74AUP2G32GM,125 pinout, 74AUP2G32GM,125 application, or 74AUP2G32GM,125 equivalent, key selection factors include its 0.8 V minimum VCC support, IOFF-enabled power-gating capability, Schmitt-trigger input hysteresis for slow-edge tolerance, and XQFN8 (SOT902-2) package compatibility with high-density PCB layouts.

Technical Context

This device implements two independent OR logic functions with Schmitt-trigger inputs on all four inputs (1A/1B/2A/2B), enabling robust operation with slow-rising or noisy signals. Each output (1Y/2Y) drives CMOS loads with rail-to-rail swing and supports IOFF state when VCC = 0 V, blocking backflow current.

It complies with JEDEC standards JESD8-12 through JESD8C across five VCC ranges and meets HBM ESD >5000 V and CDM >1000 V. The logic function follows standard OR truth table: output HIGH if ≥1 input is HIGH; LOW only when both inputs are LOW.

Key Specifications

Pinout & Package

XQFN8 package (SOT902-2): plastic ultra-thin quad flat no-lead, 1.4 × 1.2 × 0.45 mm body, 0.4 mm pitch, wettable flank terminals, thermal pad exposed on bottom for enhanced heat dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 2-input OR gate applications.

Compared with 74LVC2G32GW,125 and SN74AUP2G32DCUR, the 74AUP2G32GM,125 uniquely balances ultra-low ICC, Schmitt-trigger noise immunity, and XQFN8 thermal/space efficiency - making it optimal for miniaturized, battery-critical, and electrically noisy applications where other variants trade off one or more of these attributes.

Availability

74AUP2G32GM,125 is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control, wearable health monitoring, and smart home motion detection requiring stable component supply across extended temperature and low-power operating conditions.

Supply support for 74AUP2G32GM,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions, serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.

The 74AUP (Advanced Ultra-low Power) product line delivers sub-1 μA logic ICs optimized for energy-constrained edge devices, emphasizing ultra-low ICC, wide VCC scalability, and robust IOFF functionality for modern power-aware system architectures.

FAQ

Does 74AUP2G32GM,125 support true bidirectional operation?

No. It is a unidirectional logic gate with defined inputs (1A/1B/2A/2B) and outputs (1Y/2Y). Neither inputs nor outputs are designed for reverse current flow or bus arbitration. The IOFF feature disables outputs when VCC = 0 V but does not enable input/output role reversal.

Can 74AUP2G32GM,125 drive a 50 pF capacitive load reliably?

Yes - though propagation delay increases to ~8.5 ns at VCC = 3.0 V and CL = 30 pF (per datasheet Table 8), the device maintains valid VOH/VOL levels and timing margins up to 50 pF. For CL > 30 pF, verify setup/hold timing against your MCU's input requirements using worst-case tpd values.

Is the EPAD on SOT902-2 internally connected?

Yes - the exposed thermal pad (EPAD) is internally tied to GND per Nexperia's package drawing SOT902-2. It must be soldered to a GND plane for optimal thermal performance, mechanical stability, and ESD current shunting; floating or unconnected EPAD degrades reliability and noise immunity.

What happens to output states during VCC ramp-up?

Outputs remain in high-impedance (Hi-Z) until VCC reaches ~0.5 V, then transition to valid logic states as supply stabilizes. The IOFF circuit ensures no output contention or backfeed occurs during power sequencing - critical for safe integration into multi-rail systems with staggered power-up sequences.