Nexperia USA Inc. 74AUP2G32GN,115

Overview

74AUP2G32GN,115 from Nexperia is a dual 2-input OR gate logic IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ultra-low static current (≤1.4 μA at −40 °C to +125 °C), IOFF-enabled partial power-down protection, and propagation delay as low as 0.9 ns at VCC = 3.0 V (CL = 5 pF). It serves in battery-powered sensor interface and low-voltage microcontroller I/O expansion circuits.

For engineers reviewing the 74AUP2G32GN,115 datasheet, 74AUP2G32GN,115 pinout, 74AUP2G32GN,115 application, or 74AUP2G32GN,115 equivalent, key selection criteria include its 0.8 V minimum VCC support, IOFF leakage < ±0.75 μA during power-down, Schmitt-trigger noise immunity, and XSON8 package footprint (1.2 × 1.0 × 0.35 mm) for space-constrained PCBs.

Technical Context

This device implements two independent OR logic functions with hysteresis on all inputs, enabling robust operation with slow-rising signals and high noise margin. Its CMOS architecture ensures rail-to-rail output swing and sub-1 μA ICC at 25 °C.

The IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current and supporting hot-insertion and multi-rail system partitioning. Input overvoltage tolerance up to 3.6 V allows interfacing with higher-voltage peripherals without level shifters.

Key Specifications

Pinout & Package

XSON8 package (SOT1116): extremely thin small outline, no leads, 8-terminal surface-mount, body dimensions 1.2 mm × 1.0 mm × 0.35 mm, pin 1 indicator located below marking code 'pG' in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 2-input OR gate applications.

Compared with SN74LVC2G32DSFR and 74LVC2G32GM126, the 74AUP2G32GN,115 uniquely delivers sub-1 μA ICC at 0.8 V and guaranteed IOFF behavior - making it the only choice for battery lifetime-critical, multi-rail, or ultra-low-voltage embedded systems.

Availability

74AUP2G32GN,115 is available at Aetrix Electronics and suitable for industrial sensor interface, wearable device power sequencing, and automotive body control module applications requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for 74AUP2G32GN,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and discrete components with industry-leading reliability and quality.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and energy-constrained systems, emphasizing nanowatt static power, wide VCC scalability, and robust IO features like IOFF and overvoltage tolerance.

FAQ

Does 74AUP2G32GN,115 support true bidirectional signal routing?

No. The 74AUP2G32GN,115 is a unidirectional logic gate with defined inputs (1A/1B/2A/2B) and outputs (1Y/2Y). It lacks bus-hold, direction-control, or tri-state capability. Its IOFF feature only disables outputs during power-down - it does not enable reverse signal flow or bus arbitration functionality.

Can this device drive a 50 pF capacitive load reliably at 3.0 V?

Yes, but with timing impact: at VCC = 3.0 V and CL = 50 pF, propagation delay increases to ~12 ns (extrapolated from CL = 30 pF data of 8.5 ns max). Output drive strength remains intact (±20 mA), and VOL stays ≤0.50 V. For critical timing paths, limit CL to ≤15 pF or add series termination.

Is the Schmitt-trigger hysteresis value specified in the datasheet?

Yes - hysteresis is implicit in VIH/VIL specifications: at VCC = 3.0 V, VIH(min) = 2.0 V and VIL(max) = 0.9 V, yielding ≥1.1 V hysteresis window. This exceeds typical 0.3–0.5 V hysteresis in standard CMOS gates, directly enabling noise margins >300 mV on 3.3 V signals.

What is the maximum allowable input transition rate (Δt/ΔV)?

The datasheet specifies Δt/ΔV ≤ 200 ns/V across VCC = 0.8–3.6 V. At VCC = 1.2 V, this permits rise/fall times as slow as 240 ns; at VCC = 3.3 V, up to 660 ns. Slower edges remain valid due to Schmitt-trigger action - no minimum slew rate is enforced.