Nexperia USA Inc. 74AUP2G32GXX

Overview

74AUP2G32GXX from Nexperia is a low-power dual 2-input OR gate logic IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ICC ≤ 0.9 μA max static current and propagation delay as low as 1.0 ns at VCC = 3.3 V/CL = 5 pF, used in battery-powered sensor interface and level-shifting signal conditioning circuits.

For engineers reviewing the 74AUP2G32GXX datasheet, 74AUP2G32GXX pinout, 74AUP2G32GXX application, or 74AUP2G32GXX equivalent, this device supports partial power-down via IOFF circuitry, tolerates overvoltage inputs up to 3.6 V, and maintains high noise immunity across industrial temperature range (–40 °C to +125 °C).

Technical Context

This CMOS logic gate implements two independent OR functions with Schmitt-trigger input thresholds-ensuring robust operation with slow-rising/falling signals-and features IOFF circuitry that disables outputs during power-down to prevent backflow current. Its input voltage tolerance extends to 3.6 V regardless of VCC, enabling mixed-voltage domain interfacing.

The device complies with JEDEC standards JESD8-12 through JESD8C for multiple VCC ranges and meets HBM ESD rating >5000 V and CDM >1000 V. It is characterized across –40 °C to +125 °C with guaranteed performance at 0.8 V minimum supply.

Key Specifications

Pinout & Package

X2SON8 package (SOT1233-2): plastic thermal-enhanced extremely thin small outline, no leads, 8 terminals, body size 1.35 × 0.8 × 0.32 mm, exposed thermal pad not electrically connected.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 2-input OR gate applications.

Compared with SN74LVC2G32DBVR and 74LVC2G32GM125, the 74AUP2G32GXX uniquely supports 0.8 V operation, Schmitt-trigger noise rejection, and IOFF-enabled partial power-down-making it the sole choice for ultra-low-voltage, mixed-rail, and hot-swap-sensitive applications.

Availability

74AUP2G32GXX is available at Aetrix Electronics and suitable for industrial sensor interface, portable device power sequencing, and automotive body control modules requiring stable component supply across extended temperature and low-voltage conditions.

Supply support for 74AUP2G32GXX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP (Advanced Ultra-low Power) product line targets battery-constrained and thermally sensitive applications, emphasizing sub-1 μA static current, wide VCC scalability, and robust IO architecture for next-generation portable and automotive electronics.

FAQ

Does 74AUP2G32GXX support true bidirectional signal routing?

No. The 74AUP2G32GXX is a unidirectional logic gate with defined inputs (1A/1B/2A/2B) and outputs (1Y/2Y). It lacks internal pass-gate structure or tri-state control, so signals cannot propagate from output to input. Its IOFF feature only disables output drivers during power-down-it does not enable reverse conduction.

Can 74AUP2G32GXX be used with 0.8 V microcontroller I/O without level shifting?

Yes. The device is fully specified at VCC = 0.8 V, with VIH = 0.70 × VCC (≥0.56 V) and VIL = 0.30 × VCC (≤0.24 V), matching standard 0.8 V logic thresholds. Its Schmitt-trigger inputs further improve noise margin, making direct connection to 0.8 V MCUs viable without external translation.

What is the thermal pad connection requirement for the X2SON8 (SOT1233-2) package?

The X2SON8 package has an exposed thermal pad (pin 5 is GND; pad is non-electrical). Nexperia specifies no electrical connection-do not solder the pad to GND or any net. It serves only mechanical stability and thermal dissipation via PCB copper area, and must remain electrically isolated per datasheet layout guidance.

How does the IOFF feature behave when VCC ramps from 0 V to nominal voltage?

IOFF activates automatically when VCC drops below ~0.2 V and remains active until VCC exceeds ~0.5 V. During ramp-up, outputs stay disabled until VCC crosses the IOFF release threshold, preventing glitching or contention. This behavior is intrinsic to the internal circuitry and requires no external control signals.