Diodes Incorporated 74AUP2G32RA3-7
- Part No.:
- 74AUP2G32RA3-7
- Manufacturer:
- Diodes Incorporated
- Category:
- Gates and Inverters
- Package:
- 8-XFDFN
- Datasheet:
-
74AUP2G32RA3-7.pdf
- Description:
- IC GATE OR 2CH 2-INP DFN1210-8
- Quantity:
- Payment:

- Shipping:

Inventory:3,941
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Product details
Overview
74AUP2G32RA3-7 from Diodes Incorporated is a dual 2-input OR gate in the Advanced Ultra Low Power (AUP) CMOS logic family, designed for battery-powered portable systems. It operates from 0.8V to 3.6V, delivers ±4mA output drive at 3.0V, features IOFF partial power-down protection, and uses Schmitt-trigger inputs with ~250mV hysteresis at VCC = 3.0V for noise immunity in low-slew-rate signal paths.
For engineers reviewing the 74AUP2G32RA3-7 datasheet, 74AUP2G32RA3-7 pinout, 74AUP2G32RA3-7 application, or 74AUP2G32RA3-7 equivalent, key selection criteria include ultra-low ICC (<0.9µA), wide VCC range compatibility, IOFF-enabled system-level power sequencing, and DFN1210-8 footprint constraints in space-constrained mobile designs.
Technical Context
This device implements two independent positive-logic OR functions (Y = A + B) using push-pull CMOS outputs. Its IOFF circuit actively disables outputs during power-down to prevent back-current flow between powered and unpowered rails - critical for mixed-voltage domain interconnects in modern portable SoC subsystems.
Schmitt-trigger inputs provide defined switching thresholds and hysteresis (~250mV at 3.0V), enabling reliable operation with slow-rising signals from sensors or legacy interfaces. Propagation delay ranges from 1.0ns (typ, 3.3V, CL=5pF) to 8.5ns (max, -40°C to +125°C, CL=30pF), supporting timing-critical control logic in low-power microcontroller peripherals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8V to 3.6V - enables direct interface with sub-1V logic domains and 3.3V I/O without level shifters |
| IOFF Leakage | ±0.2µA max at 0V - prevents destructive current flow when one supply rail is powered down |
| ICC Static Current | <0.9µA at 25°C - extends battery life in always-on sensor monitoring circuits |
| Output Drive | ±4mA at VCC = 3.0V - sufficient to drive multiple CMOS inputs or small capacitive loads (≤15pF) |
| Input Hysteresis | ~250mV at VCC = 3.0V - rejects noise on slow-switching lines such as reset or enable signals |
| tpd (Typ) | 2.1ns at 3.3V, CL = 5pF - supports >200MHz toggle rates in low-capacitance control paths |
| Cpd | 6.0pF at 3.3V - contributes directly to dynamic power: Pdyn ≈ Cpd × V² × f |
Pinout & Package
X2-DFN1210-8 package: 1.2mm × 1.0mm × 0.35mm body, 0.3mm lead pitch, bottom thermal pad, no leads - optimized for high-density PCB layouts and thermal dissipation in thin-profile handheld devices.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A, 1B, 2A, 2B | Input (Gate 1 & 2) | CMOS-compatible digital inputs with Schmitt-trigger action; tolerate slow edges and noise |
| 1Y, 2Y | Output (Gate 1 & 2) | Push-pull CMOS outputs capable of sourcing/sinking ±4mA; support rail-to-rail swing |
| VCC | Supply Voltage | Primary power rail (0.8–3.6V); powers internal logic and output drivers |
| GND | Ground Reference | Return path for all currents; must be low-impedance to minimize ground bounce |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC < 0.9µA enables multi-year operation on coin-cell batteries in IoT wake-up logic |
| IOFF partial power-down | Blocks back-current during VCC ramp-down - essential for hot-plug and power-gating architectures |
| Schmitt-trigger inputs | 250mV hysteresis at 3.0V ensures clean transitions on noisy or RC-filtered control lines |
| Wide VCC compatibility | 0.8–3.6V operation supports direct connection to 1.2V core, 1.8V I/O, and 3.3V peripheral rails |
| ESD robustness | 2kV HBM / 1kV CDM rating reduces need for external protection in consumer-grade assemblies |
Applications
| Mobile Device Power Sequencing | Low-Power Sensor Interface |
|---|---|
|
Use Scenario: Coordinating power-up order of PMIC rails and application processor cores in smartphones. IC Role / Device Role / Timing Role: Dual OR gate combines multiple enable signals (e.g., battery OK + thermal OK) into a single system-ready flag. Use Value: IOFF prevents leakage-induced voltage rise on unpowered rails during staggered startup sequences. |
Use Scenario: Debouncing mechanical switches or conditioning analog comparator outputs in wearable health monitors. IC Role / Device Role / Timing Role: Schmitt-trigger inputs clean up slow-rising sensor interrupt signals before routing to MCU GPIO. Use Value: 250mV hysteresis eliminates chatter without external RC networks, saving board space and BOM cost. |
| USB-C Port Controller Logic | Industrial Edge Node Status Aggregation |
|
Use Scenario: Generating USB port power-enable signals based on CC line detection and policy engine status. IC Role / Device Role / Timing Role: OR gate merges USB PD negotiation success and overcurrent fault clearance flags. Use Value: Push-pull outputs drive 3.3V enable lines directly - no pull-up resistors needed, reducing standby current. |
Use Scenario: Consolidating fault indicators (temperature, voltage, comms loss) into a single "system alarm" output for PLC input modules. IC Role / Device Role / Timing Role: Dual gate performs OR-reduction across three independent sensor alarms. Use Value: 0.8V minimum VCC allows operation from backup supercapacitor during main power failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 2-input OR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74AUP2G32DSFR | TSSOP-8 package (2.0mm × 1.25mm); higher θJA (320°C/W); no thermal pad | Less suitable for thermally constrained handheld PCBs; easier hand-soldering | Select when manual assembly or thermal margin >100°C/W is acceptable |
| 74LVC2G32GM,132 | NXP part; 1.65–5.5V VCC range; higher ICC (1.5µA typ); no IOFF | Not usable in partial power-down systems; requires external isolation for mixed-rail domains | Select only for fixed 3.3V/5V systems where IOFF is unnecessary |
Compared with SN74AUP2G32DSFR and 74LVC2G32GM,132, the 74AUP2G32RA3-7 uniquely combines ultra-low ICC, IOFF, and DFN1210-8 thermal performance - making it optimal for miniaturized, battery-operated devices requiring robust power sequencing.
Availability
74AUP2G32RA3-7 is available at Aetrix Electronics and suitable for mobile device power sequencing, low-power sensor interface, USB-C port controller logic, and industrial edge node status aggregation requiring stable component supply across long-lifecycle consumer and industrial programs.
Supply support for 74AUP2G32RA3-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-efficiency power management, signal integrity, and precision timing solutions for consumer, industrial, and automotive markets.
The AUP logic family targets ultra-low-power portable electronics, delivering sub-1µA static current and wide-VCC operation to extend battery life while maintaining robust noise immunity and system-level power sequencing capability.
FAQ
Does 74AUP2G32RA3-7 support true bidirectional signal flow?
No. It is a unidirectional logic gate with defined inputs (1A/1B/2A/2B) and outputs (1Y/2Y). The IOFF feature disables outputs during power-down but does not enable reverse signal propagation. Inputs remain high-impedance CMOS nodes regardless of VCC state.
Can unused inputs be left floating?
No. Per Diodes' Recommended Operating Conditions (Note 8), all unused inputs must be tied to VCC or GND. Floating inputs cause increased ICC, potential oscillation, and unpredictable output states due to CMOS threshold sensitivity - especially critical in ultra-low-power designs.
What is the maximum capacitive load this device can drive reliably?
Electrical characteristics are specified up to CL = 30pF. At 3.3V, tpd increases from 2.1ns (CL = 5pF) to 8.5ns (CL = 30pF, -40°C to +125°C). For timing-critical paths, keep CL ≤15pF; for non-critical enable/control lines, 30pF is supported with verified setup/hold margins.
Is the X2-DFN1210-8 package compatible with standard reflow profiles?
Yes. The package is qualified for JEDEC J-STD-020D moisture sensitivity level 1 (MSL1) and supports standard Pb-free reflow profiles (peak 260°C, 20–40 sec above 217°C). Thermal pad soldering requires controlled stencil aperture (0.25mm × 0.25mm) and 50% paste coverage to ensure mechanical reliability.
74AUP2G32RA3-7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- OR Gate
- Number of Circuits:
- 2
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 6.4ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- X2-DFN1210-8
74AUP2G32RA3-7 FAQ
1.How can I place an order for 74AUP2G32RA3-7 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G32RA3-7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G32RA3-7 reliable?
The price and inventory of 74AUP2G32RA3-7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G32RA3-7 is usually 5 days.
3.What payment methods are accepted for 74AUP2G32RA3-7?
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4.How is shipping managed for 74AUP2G32RA3-7?
74AUP2G32RA3-7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G32RA3-7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G32RA3-7?
For technical support, including 74AUP2G32RA3-7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G32RA3-7 requirements.
6.How does Aetrix verify that 74AUP2G32RA3-7 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G32RA3-7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G32RA3-7 meets industry standards.
7.What is the process for return or replacement of 74AUP2G32RA3-7?
All 74AUP2G32RA3-7 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G32RA3-7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G32RA3-7 part is unused and in its original packaging.
Return procedure for 74AUP2G32RA3-7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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