Nexperia USA Inc. 74AUP2G3404GF,125

Overview

74AUP2G3404GF,125 from Nexperia is a dual-function CMOS logic device integrating one non-inverting buffer (1A→1Y) and one inverting buffer (2A→2Y), both with Schmitt-trigger inputs for noise immunity across 0.8 V–3.6 V supply range. It delivers ultra-low static current (≤0.9 μA max), IOFF-enabled partial power-down protection, and propagation delays as low as 1.1 ns at 3.6 V/CL=5 pF - enabling reliable signal conditioning in battery-powered IoT sensor interfaces and low-voltage microcontroller I/O expansion.

For engineers reviewing the 74AUP2G3404GF,125 datasheet, 74AUP2G3404GF,125 pinout, 74AUP2G3404GF,125 application, or 74AUP2G3404GF,125 equivalent, this device serves as a space-optimized, rail-to-rail compatible logic gate for level-shifting, waveform shaping, and bus driving in compact portable electronics where supply voltage flexibility and leakage control are critical.

Technical Context

The 74AUP2G3404GF,125 implements two independent single-gate functions in one die: a true buffer (non-inverting) and an inverter (inverting), each with hysteresis-equipped Schmitt-trigger inputs ensuring clean switching despite slow-rising signals. Its IOFF circuit actively disables outputs during VCC = 0 V, blocking backflow current to prevent system-level latch-up in hot-swap or multi-rail environments.

All inputs tolerate up to 3.6 V regardless of VCC (0.8–3.6 V), supporting mixed-voltage interfacing without external level shifters. Dynamic performance is characterized across four load capacitances (5–30 pF) and three temperature ranges (−40 °C to +125 °C), with propagation delay tightly specified down to 1.0 ns (min) at 3.0–3.6 V.

Key Specifications

Pinout & Package

XSON6 package (SOT886): plastic extremely thin small outline, no leads, 6-terminal surface-mount with 1.0 mm × 1.45 mm × 0.5 mm body and wettable flank terminals for automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-buffer/inverter applications.

Compared with 74LVC2G3404GW and NLX2G3404MUTAG, the 74AUP2G3404GF,125 uniquely combines sub-1 μA static current, Schmitt-trigger robustness, and 0.5 mm pitch XSON6 packaging - making it optimal for miniaturized, ultra-low-power, noise-prone applications where every nanoamp and square millimeter matters.

Availability

74AUP2G3404GF,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable device power management, automotive body control modules, and low-power microcontroller I/O expansion requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for 74AUP2G3404GF,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.

The 74AUP (Advanced Ultra-low Power) family targets battery-constrained and thermally sensitive applications, delivering industry-leading static/dynamic power efficiency without compromising speed or noise immunity.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP2G3404GF,125 inputs are overvoltage tolerant up to 3.6 V regardless of VCC state. When VCC = 0 V, VI may safely range from −0.5 V to +3.6 V per Absolute Maximum Ratings Table 6, and IOFF leakage remains ≤±0.75 μA - enabling safe "live insertion" into powered-backplane systems.

Does the device support mixed-voltage operation between input and output rails?

No - the 74AUP2G3404GF,125 has a single VCC supply; all outputs swing between GND and VCC. However, its inputs accept voltages up to 3.6 V independently of VCC (e.g., 1.8 V VCC with 3.3 V input), enabling level translation from higher-voltage sources into lower-voltage logic domains without external components.

How does the Schmitt-trigger hysteresis vary with supply voltage?

Hysteresis width (ΔV = V_IH − V_IL) scales approximately linearly with VCC: at VCC = 0.8 V, ΔV ≈ 0.24 V; at VCC = 3.6 V, ΔV ≈ 1.1 V. This maintains consistent noise margin percentage (≈30%) across the full 0.8–3.6 V operating range, as confirmed in Tables 8 and 10 of the datasheet.

Can the 74AUP2G3404GF,125 drive a 50 pF capacitive load reliably?

While not explicitly characterized beyond 30 pF in the datasheet, propagation delay increases predictably with load capacitance (e.g., +2.9 ns at 30 pF vs. +1.1 ns at 5 pF, VCC = 3.6 V). Driving 50 pF is feasible at reduced speed (≥10 MHz toggle rate), but output rise/fall times will exceed 5 ns - verify signal integrity with IBIS simulation or bench testing for timing-critical use cases.