NXP Semiconductors 74AUP2G3404GM,125

Overview

74AUP2G3404GM,125 from Nexperia is a dual-function low-power logic device integrating one Schmitt-trigger buffer (1A→1Y) and one Schmitt-trigger inverter (2A→2Y) in a single XSON6 package. It operates across 0.8 V to 3.6 V supply, delivers ICC ≤ 0.9 μA max static current, supports IOFF partial power-down, and is rated for −40 °C to +125 °C ambient. It enables robust signal conditioning in battery-powered sensor interfaces and voltage-level agnostic control paths.

For engineers reviewing the 74AUP2G3404GM,125 datasheet, 74AUP2G3404GM,125 pinout, 74AUP2G3404GM,125 application, or 74AUP2G3404GM,125 equivalent, this device is selected for ultra-low quiescent power, rail-tolerant inputs up to 3.6 V, Schmitt-trigger noise immunity on both channels, and guaranteed operation down to 0.8 V - critical for mixed-voltage IoT node design and always-on wake-up circuitry.

Technical Context

This dual-channel CMOS logic IC implements independent Schmitt-trigger input stages on both 1A and 2A pins, enabling reliable signal reconstruction from slow-rising or noisy waveforms across its full 0.8–3.6 V VCC range. Each channel features separate output drive capability with VOH ≥ VCC − 0.11 V (at −20 μA) and VOL ≤ 0.50 V (at 4 mA), ensuring interoperability with downstream 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic families.

The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA max and preventing bus contention during hot-insertion or partial system shutdown. Propagation delay is load- and voltage-dependent: tpd = 1.1–4.3 ns (CL = 5–30 pF, VCC = 3.0–3.6 V), with CPD = 4.0 pF enabling precise dynamic power estimation via PD = CPD × VCC² × fi × N.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886), no leads, 6 terminals, body dimensions 1.0 mm × 1.45 mm × 0.5 mm. Pin 1 index located on lower-left corner below marking code "aZ".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-buffer/inverter applications.

Compared with 74LVC2G3404GM and NLX2G3404XV6T2G, the 74AUP2G3404GM,125 uniquely combines ultra-low ICC (0.9 μA), Schmitt-trigger noise immunity, and IOFF - making it the sole option for battery-critical, mixed-voltage, and hot-swap-capable designs requiring guaranteed zero-backflow behavior.

Availability

74AUP2G3404GM,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, IoT node wake-up circuits, USB-C port detection logic, and automotive body control modules requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for 74AUP2G3404GM,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume applications.

The 74AUP (Advanced Ultra-low Power) family targets energy-constrained systems - designed specifically for battery-powered wearables, sensor nodes, and always-on subsystems where nanowatt static power and rail-to-rail voltage flexibility are mandatory.

FAQ

What is the maximum capacitive load the 74AUP2G3404GM,125 can drive while maintaining specified propagation delay?

The device is characterized up to CL = 30 pF across all VCC conditions. At VCC = 3.3 V, tpd remains ≤7.2 ns (1A→1Y or 2A→2Y) with CL = 30 pF. Driving loads >30 pF increases delay nonlinearly and may exceed timing budgets - external buffer staging is recommended beyond this limit.

Does the IOFF feature activate automatically when VCC drops below a threshold, or must it be controlled externally?

IOFF activates autonomously when VCC = 0 V - no external control signal is required. The internal circuitry disables both outputs (1Y and 2Y) as VCC collapses, limiting leakage to ±0.75 μA regardless of input/output voltage states. This behavior is intrinsic and requires no enable pin or configuration.

Can 74AUP2G3404GM,125 safely interface a 5 V microcontroller output to a 1.2 V FPGA input?

No - while inputs tolerate up to 3.6 V, they are not 5 V tolerant. A 5 V signal exceeds the absolute maximum VI rating (−0.5 V to +4.6 V) and risks permanent damage. Use a dedicated level translator (e.g., TXB0102) or add a series resistor + clamp diode if interfacing 5 V sources.

How does the Schmitt-trigger hysteresis vary with supply voltage, and what is its minimum guaranteed value?

Hysteresis is proportional to VCC: typical 0.1 × VCC, with guaranteed minimum ΔV = V_IH(min) − V_IL(max). At VCC = 0.8 V, min hysteresis is 0.12 V; at VCC = 3.6 V, it reaches 0.44 V. This ensures consistent noise rejection across the entire operating range without recalibration.