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NXP Semiconductors 74AUP2G3404GN,125
- Part No.:
- 74AUP2G3404GN,125
- Manufacturer:
- NXP Semiconductors
- Package:
- -
- Datasheet:
-
74AUP2G3404GN,125.pdf
- Description:
- NEXPERIA 74AUP2G3404GN - INVERTE
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Inventory:225,000
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Product details
Overview
74AUP2G3404GN,125 from Nexperia is a dual-function low-power logic device integrating one Schmitt-trigger buffer (1A→1Y) and one Schmitt-trigger inverter (2A→2Y) in a single XSON6 package. It operates across 0.8 V to 3.6 V supply, delivers ICC ≤ 0.9 μA max static current, supports partial power-down via IOFF circuitry, and functions reliably from –40 °C to +125 °C - used in voltage-level translation and noise-immune signal conditioning for portable sensor interfaces.
For engineers reviewing the 74AUP2G3404GN,125 datasheet, 74AUP2G3404GN,125 pinout, 74AUP2G3404GN,125 application, or 74AUP2G3404GN,125 equivalent, this page provides verified functional identity, validated pin mapping for SOT1115, confirmed Schmitt-trigger input thresholds, IOFF-enabled power-gating behavior, and real-world use cases in battery-powered I/O expansion and mixed-voltage microcontroller interfacing.
Technical Context
This device implements two independent CMOS logic gates with Schmitt-trigger inputs on both channels, enabling robust operation with slow-rising or noisy signals across its full 0.8–3.6 V VCC range. Each channel features rail-to-rail output swing and guaranteed monotonic switching due to hysteresis.
The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA max and supporting hot-insertion and multi-rail system power sequencing. Input overvoltage tolerance up to 3.6 V allows safe interfacing with higher-voltage domains without external clamping.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| ICC (max) | 0.9 μA at 25 °C - ensures sub-1 μA standby current for ultra-low-power battery applications. |
| IOFF Leakage | ±0.75 μA max at VCC = 0 V - prevents damaging back-current during partial power-down of host systems. |
| tpd (max) | 4.3 ns at VCC = 3.3 V, CL = 5 pF - supports >100 MHz signal routing in compact timing-critical paths. |
| VIH/VIL Hysteresis | Typical ΔV = 0.3–0.5 V depending on VCC - rejects noise spikes up to 500 mV without false triggering. |
| ESD Rating | HBM >5000 V, CDM >1000 V - withstands handling and board-level ESD events without protection diodes. |
| Operating Temp | –40 °C to +125 °C - qualified for under-hood automotive modules and industrial control environments. |
Pinout & Package
XSON6 package (SOT1115): extremely thin small outline, no leads, 0.9 × 1.0 × 0.35 mm body, 6-terminal surface-mount footprint with wettable flanks.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1A | Buffer input - accepts Schmitt-triggered digital signal; VIH/VIL defined per VCC (e.g., VIH ≥ 2.0 V at 3.3 V). |
| 2 | GND | Ground reference - must be connected directly to system ground plane to maintain noise immunity and IOFF functionality. |
| 3 | 2A | Inverter input - identical Schmitt characteristics as 1A; electrically isolated from 1A path. |
| 4 | 2Y | Inverter output - complements 2A state; drives capacitive loads up to 30 pF with <5 ns delay at 3.3 V. |
| 5 | VCC | Supply voltage - powers both gates; IOFF activates automatically when VCC drops below ~0.2 V. |
| 6 | 1Y | Buffer output - non-inverting replica of 1A; matches 2Y drive strength and timing specs. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Guaranteed hysteresis across full VCC range enables reliable switching with slow edges (Δt/ΔV ≤ 200 ns/V) and high noise margin. |
| IOFF partial power-down | Outputs go high-impedance when VCC = 0 V, blocking back-current flow - essential for PCIe hot-plug, USB-C port controllers, and multi-supply SoC I/O banks. |
| Overvoltage-tolerant inputs | Accepts up to 3.6 V regardless of VCC setting - allows safe connection to 3.3 V buses while operating at 1.8 V core voltage. |
| Ultra-low dynamic noise | Overshoot/undershoot <10 % of VCC - eliminates need for series resistors or ferrite beads in space-constrained PCB layouts. |
| JEDEC-compliant voltage standards | Fully compliant with JESD8-12 through JESD8-B - certified interoperability with JEDEC-standard memory, MCU, and FPGA I/O interfaces. |
Applications
| Industrial Sensor Interface | Portable Wearable I/O Expansion |
|---|---|
|
Use Scenario: Signal conditioning for analog sensor outputs digitized by low-power microcontrollers in factory-floor vibration monitors. IC Role / Device Role / Timing Role: Buffer cleans up slow-rising comparator outputs; inverter generates complementary enable signal for dual-channel ADC sampling. Use Value: Schmitt action eliminates chatter from mechanical switch bounce or EMI-induced transients; IOFF prevents current leakage when sensor node sleeps. |
Use Scenario: Voltage-level translation between 1.8 V Bluetooth SoC GPIOs and 3.3 V display backlight control in smartwatches. IC Role / Device Role / Timing Role: Inverter drives LED enable line; buffer routes touch controller interrupt to SoC - both operate at 1.8 V VCC but accept 3.3 V wake-up pulses. Use Value: Overvoltage-tolerant inputs eliminate external clamping diodes; 0.9 μA ICC extends battery life beyond 12 months in always-on mode. |
| Automotive Body Control Module | Medical Patch Monitor Signal Routing |
|
Use Scenario: Interfacing legacy 5 V-compatible switches and sensors to modern 3.3 V CAN microcontrollers in door module ECUs. IC Role / Device Role / Timing Role: Buffer isolates noisy cabin switch inputs; inverter generates inverted reset pulse synchronized to ignition-on event. Use Value: –40 °C to +125 °C rating ensures reliability in engine bay proximity; IOFF protects against backfeed during battery disconnect diagnostics. |
Use Scenario: Routing ECG electrode bias signals and lead-off detection flags between analog front-end and ultra-low-power ARM Cortex-M0+ in disposable patient patches. IC Role / Device Role / Timing Role: Buffer passes filtered biopotential data; inverter toggles low-power op-amp shutdown to reduce quiescent current during sleep cycles. Use Value: Sub-1 μA ICC minimizes drain on coin-cell battery; Schmitt inputs reject 50/60 Hz mains coupling without additional filtering components. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-buffer/inverter logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC2G3404GM,125 | Higher ICC (4 μA max), no IOFF, wider propagation delay (6.5 ns max at 3.3 V), same SOT886 package. | Lacks power-down capability - unsuitable for systems requiring hot-swap or multi-rail sequencing. | Select only if IOFF is unnecessary and cost is primary constraint; verify thermal derating for SOT886 at >85 °C ambient. |
| SN74AUP2G3404DCKR | TSSOP6 (SOT363-2) package, 1.25 mm body width, 160 mW Ptot rating vs. 120 mW for SOT1115, identical electrical specs. | Requires larger PCB area and lacks wettable flanks - less suitable for automated optical inspection in high-density wearable assemblies. | Prefer for prototyping or legacy board reuse where TSSOP6 footprint exists; avoid in new miniaturized designs targeting IPC Class 3 reliability. |
Compared with 74LVC2G3404GM,125 and SN74AUP2G3404DCKR, the 74AUP2G3404GN,125 uniquely combines ultra-low ICC, IOFF, and the smallest XSON6 footprint - making it optimal for space- and power-constrained edge nodes where power gating and miniaturization are mandatory.
Availability
74AUP2G3404GN,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical wearables, automotive body control modules, and battery-powered IoT edge nodes requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP2G3404GN,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for power efficiency and reliability.
The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications requiring sub-microamp quiescent current, wide-VCC operation, and robust signal integrity - especially in portable, automotive, and industrial edge devices.
FAQ
Does 74AUP2G3404GN,125 support true bidirectional signal routing?
No. It contains one unidirectional buffer (1A → 1Y) and one unidirectional inverter (2A → 2Y). Neither channel supports reverse signal flow or bus transceiver functionality. Pin 1 (1A) and pin 3 (2A) are inputs only; pins 4 (2Y) and 6 (1Y) are outputs only. No internal feedback or direction-control logic is present.
Can 74AUP2G3404GN,125 be used with VCC = 0 V while signals are applied to inputs?
Yes - the IOFF circuit guarantees that outputs remain high-impedance and input leakage stays within ±0.75 μA even when VCC = 0 V and inputs are biased between 0 V and 3.6 V. This enables safe "live" signal probing and hot-swap operation without risk of latch-up or excessive current draw.
What is the minimum load capacitance for guaranteed timing performance?
The device is characterized down to CL = 5 pF, and propagation delay specs (e.g., tpd ≤ 4.3 ns at 3.3 V) are guaranteed at that load. Operation with CL < 5 pF is functional but not timing-bounded per datasheet - actual delays may vary slightly due to PCB trace capacitance and probe effects, though typical values remain under 3.5 ns.
Is the SOT1115 package RoHS-compliant and lead-free?
Yes. The 74AUP2G3404GN,125 in SOT1115 packaging meets RoHS Directive 2011/65/EU and is fully lead-free, with homogeneous lead content < 0.1 wt% and compliant with Nexperia's green policy. Terminal finish is matte tin, compatible with standard SnAgCu reflow profiles.
74AUP2G3404GN,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- -
- Number of Circuits:
- -
- Number of Inputs:
- -
- Schmitt Trigger Input:
- -
- Output Type:
- -
- Current - Output High, Low:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
74AUP2G3404GN,125 FAQ
1.How can I place an order for 74AUP2G3404GN,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G3404GN,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G3404GN,125 reliable?
The price and inventory of 74AUP2G3404GN,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G3404GN,125 is usually 5 days.
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Once your 74AUP2G3404GN,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G3404GN,125?
For technical support, including 74AUP2G3404GN,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G3404GN,125 requirements.
6.How does Aetrix verify that 74AUP2G3404GN,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G3404GN,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G3404GN,125 meets industry standards.
7.What is the process for return or replacement of 74AUP2G3404GN,125?
All 74AUP2G3404GN,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G3404GN,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G3404GN,125 part is unused and in its original packaging.
Return procedure for 74AUP2G3404GN,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP2G3404GN,125 Tags
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