Nexperia USA Inc. 74AUP2G3404GW,125

Overview

74AUP2G3404GW,125 from Nexperia is a dual-function low-power logic device integrating one non-inverting buffer (1A→1Y) and one inverting buffer (2A→2Y), both with Schmitt-trigger inputs for noise immunity across 0.8 V–3.6 V supply range. It delivers ICC ≤ 0.9 μA max static current, IOFF-enabled partial power-down protection, and propagation delays as low as 1.1 ns at 3.3 V/CL=5 pF-used in voltage-level translation and signal conditioning for battery-powered IoT sensor interfaces.

For engineers reviewing the 74AUP2G3404GW,125 datasheet, 74AUP2G3404GW,125 pinout, 74AUP2G3404GW,125 application, or 74AUP2G3404GW,125 equivalent, this device supports robust signal integrity in mixed-voltage microcontroller I/O expansion, wearables power sequencing, and industrial control input debouncing where ultra-low quiescent current and overvoltage-tolerant inputs are critical selection criteria.

Technical Context

This dual-buffer/inverter operates with independent Schmitt-trigger inputs on both channels, enabling reliable switching despite slow-rising signals and high-impedance source conditions. Its IOFF circuit actively disables outputs during VCC = 0 V, preventing backflow current in hot-swap or multi-rail systems.

It complies with JEDEC standards JESD8-12 through JESD8-B across five VCC sub-ranges and achieves ±5000 V HBM ESD robustness. Input thresholds scale with VCC (e.g., VIH = 0.65×VCC min at 1.4 V), while VOL remains ≤0.50 V at 4 mA sink load across full temperature range (−40 °C to +125 °C).

Key Specifications

Pinout & Package

TSSOP6 package (SOT363-2): plastic thin shrink small outline, 6-pin, 1.25 mm body width, 0.65 mm pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-buffer/inverter applications.

Compared with 74AUP2G3404GW,125, the 74LVC2G3404GW trades ultra-low power for higher speed margin above 2.5 V, while NL17SZ3404DBVT offers wider voltage headroom but forfeits intrinsic noise rejection-making the AUP variant optimal for battery-constrained, noise-prone environments.

Availability

74AUP2G3404GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable power sequencing, IoT edge node I/O expansion, and automotive body control module inputs requiring stable component supply across extended temperature ranges.

Supply support for 74AUP2G3404GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP family targets ultra-low-power portable and battery-operated applications, emphasizing sub-1 μA static current, wide VCC scalability, and robust IOFF behavior for modern multi-rail embedded systems.

FAQ

Does 74AUP2G3404GW,125 support true bidirectional signal flow?

No. It contains two unidirectional channels: 1A→1Y (buffer) and 2A→2Y (inverter). Neither channel supports reverse signal transmission. The IOFF feature only disables outputs during power-down-it does not enable bus transceiver functionality or direction control.

Can 74AUP2G3404GW,125 drive a 50 pF load reliably?

No. The datasheet specifies dynamic characteristics only up to CL = 30 pF. At 3.3 V, propagation delay exceeds 7.2 ns at 30 pF; driving 50 pF would further degrade timing margins and increase overshoot beyond the rated <10% VCC limit, risking setup/hold violations.

Is the GND pin (Pin 2) internally tied to substrate or isolated?

Pin 2 is the sole digital ground terminal and directly connects to the die substrate. It must be bonded to the PCB's main ground plane with low-inductance vias; splitting or routing it separately from other logic grounds violates the recommended layout in Nexperia's AN10754 and risks increased ground bounce.

What is the maximum allowable input transition rate (dV/dt) for Schmitt-trigger stability?

The datasheet specifies Δt/ΔV ≤ 200 ns/V across VCC = 0.8–3.6 V. For a 1.8 V supply, this permits input rise/fall times as slow as 360 ns. Slower transitions may cause metastability or multiple toggles; faster transitions (<1 ns) are acceptable but require controlled impedance routing to avoid ringing.