Nexperia USA Inc. 74AUP2G3407GWH

Overview

74AUP2G3407GWH from Nexperia is a dual-output low-power logic buffer IC featuring one standard CMOS output (1Y) and one open-drain output (2Y), operating across 0.8 V to 3.6 V supply range. It integrates Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and supports industrial temperature range (−40 °C to +125 °C) in TSSOP6 package. Used in voltage-level translation and I²C bus interface conditioning.

For engineers reviewing the 74AUP2G3407GWH datasheet, 74AUP2G3407GWH pinout, 74AUP2G3407GWH application, or 74AUP2G3407GWH equivalent, this page delivers verified functional identity, validated pin roles, confirmed static/dynamic specs at multiple VCC levels, and real-world use context for low-voltage signal buffering with mixed-output drive capability.

Technical Context

The device implements two independent buffer paths: 1A→1Y (push-pull, rail-to-rail) and 2A→2Y (open-drain, requires external pull-up). Schmitt-trigger inputs ensure robust operation with slow-rising signals across full VCC range. IOFF circuitry actively disables both outputs when VCC = 0 V, blocking backflow current during partial power-down.

Propagation delay varies with load capacitance and supply voltage - e.g., 1.4 ns typical (1A→1Y, CL = 5 pF, VCC = 3.3 V) and 2.1 ns typical (2A→2Y, same conditions). Power dissipation capacitance is 4.0 pF (1Y) and 1.2 pF (2Y) at VCC = 3.3 V, enabling accurate dynamic power estimation.

Key Specifications

Pinout & Package

TSSOP6 (SOT363-2) package: plastic thin shrink small outline, 6-lead, 1.25 mm body width, 0.65 mm pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output buffer applications.

Compared with 74LVC2G3407GW and SN74LVC1G34DBVR, the 74AUP2G3407GWH uniquely combines ultra-low ICC, Schmitt-trigger inputs, and dual-output topology in one TSSOP6 footprint - making it optimal for space-constrained, battery-sensitive, and electrically noisy applications where both push-pull and open-drain drive are required.

Availability

74AUP2G3407GWH is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C bus translation, low-power wake-up circuits, and LED indicator drivers requiring stable component supply across extended temperature ranges.

Supply support for 74AUP2G3407GWH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization.

This device belongs to the 74AUP (Advanced Ultra-low Power) logic family, designed specifically for battery-powered and energy-sensitive applications demanding sub-microamp quiescent current and wide-VCC interoperability.

FAQ

Can 74AUP2G3407GWH drive a 10 kΩ pull-up resistor on its 2Y output?

Yes. With 20 mA maximum sink current and VOL ≤0.50 V at VCC = 3.3 V, the 2Y output can reliably drive a 10 kΩ pull-up to 3.3 V (resulting in ~0.33 mA load), well within its specified capability and ensuring solid LOW-level assertion.

Does the IOFF feature activate automatically when VCC drops below a threshold?

Yes. The IOFF circuit engages when VCC falls near 0 V - specifically, leakage remains bounded (±0.75 μA max) even when VCC = 0 V and inputs/outputs are biased up to 3.6 V. No enable pin or external control is required; it is inherent to the silicon design.

What is the maximum capacitive load supported on 1Y without violating propagation delay specs?

The datasheet specifies tpd up to CL = 30 pF across all VCC and temperature ranges. At VCC = 3.3 V and Tamb = +125 °C, tpd remains ≤6.7 ns (1A→1Y), confirming stable operation with 30 pF total load - including PCB trace, probe, and downstream input capacitance.

Is the 74AUP2G3407GWH pin-compatible with other 74AUP2Gxxx variants in TSSOP6?

No. While many 74AUP2Gxxx devices use SOT363-2, pin functions differ significantly - e.g., 74AUP2G00 uses pins 1/2/4/5 for inputs/outputs, whereas 74AUP2G3407GWH assigns pins 1/3/4/6 to 1A/2A/2Y/1Y. Always verify pin mapping per device datasheet before layout reuse.