NXP Semiconductors 74AUP2G34GF,132
- Part No.:
- 74AUP2G34GF,132
- Manufacturer:
- NXP Semiconductors
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP2G34GF,132.pdf
- Description:
- IC BUFF DL LOW PWR N-INV 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:73,750
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Product details
Overview
74AUP2G34GF,132 from NXP Semiconductors is a dual non-inverting buffer IC in ultra-low-power CMOS technology, operating from 0.8 V to 3.6 V supply, with typical propagation delay of 2.5 ns at 3.3 V and 30 pF load, used in portable logic interfacing and level translation between mixed-voltage domains.
For engineers reviewing the 74AUP2G34GF,132 datasheet, 74AUP2G34GF,132 pinout, 74AUP2G34GF,132 application, or 74AUP2G34GF,132 equivalent, key selection criteria include supply voltage range, output drive strength (±4 mA at VCC = 3.3 V), input hysteresis for noise immunity, and guaranteed operation down to 0.8 V for battery-powered systems.
Technical Context
This device implements two independent single-bit buffers with Schmitt-trigger inputs on both channels, enabling robust signal conditioning in noisy environments. Each channel features rail-to-rail output swing and supports I2C bus-compatible voltage levels when operated at 1.8 V or 3.3 V.
The AUP family uses advanced silicon process to achieve sub-1 µA static current at 25 °C and full functionality across industrial temperature range (–40 °C to +125 °C), making it suitable for always-on sensor interface and low-duty-cycle wake-up circuits.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters |
| Propagation Delay (tPD) | 2.5 ns max at VCC = 3.3 V, CL = 30 pF - supports >200 MHz toggle rates in short-path routing |
| Output Drive (IOH/IOL) | ±4 mA at VCC = 3.3 V - sufficient to drive two 74LVC inputs or one 50 Ω transmission line |
| Quiescent Current (ICC) | 0.9 µA typical at 25 °C - allows integration into nano-power subsystems without compromising sleep current budget |
| Input Hysteresis (ΔVIN) | 300 mV typical - rejects EMI and contact bounce in push-button or switch-sense applications |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood automotive and industrial control cabinet deployment |
Pinout & Package
Supplied in a 6-pin XSON6 (1.45 × 1.0 mm) leadless package with exposed thermal pad, compatible with standard reflow profiles and IPC-7351B footprint SOT886.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | A1 (Input) | Non-inverting digital input for first buffer channel; accepts 0.7×VCC high threshold with hysteresis |
| 2 | GND | Ground reference for both buffers and internal bias network; must be low-impedance connection |
| 3 | Y1 (Output) | Push-pull CMOS output with rail-to-rail swing; drives capacitive loads up to 50 pF |
| 4 | Y2 (Output) | Independent push-pull output; electrically isolated from Y1 except shared VCC and GND |
| 5 | VCC | Single positive supply for both buffers; decoupling capacitor (100 nF) required within 3 mm |
| 6 | A2 (Input) | Second non-inverting input; identical electrical behavior to A1, supports asynchronous signal routing |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low dynamic power consumption | Typical 0.5 µW per buffer at 1 MHz toggle rate and 1.8 V supply - extends coin-cell battery life beyond 10 years |
| Schmitt-trigger inputs | Guaranteed 300 mV hysteresis window - eliminates false triggering from slow-rising signals like thermistor dividers or mechanical switches |
| IOFF partial power-down mode | Outputs go high-impedance when VCC = 0 V - prevents back-driving during hot insertion or power sequencing |
| ESD protection | HBM ±2000 V - meets IEC 61000-4-2 Level 2 for handheld and field-deployable equipment |
Applications
| Industrial Sensor Interface | Portable Medical Device Logic |
|---|---|
Use Scenario: Interfacing analog sensor outputs (e.g., RTD bridge amplifier) to microcontroller ADC trigger lines with slow edge rates. IC Role / Device Role / Timing Role: Signal conditioning buffer with hysteresis to clean up noisy, low-slew-rate analog comparator outputs before digital sampling. Use Value: Eliminates external RC filters and reduces firmware debouncing overhead by providing deterministic switching thresholds. | Use Scenario: Level-shifting between 1.8 V wearable SoC GPIOs and 3.3 V display backlight control circuitry. IC Role / Device Role / Timing Role: Bidirectional voltage-domain translator supporting both rising and falling edge integrity without direction control pins. Use Value: Enables single-supply design with no external pull-ups or level-shifter ICs, reducing BOM count by one component. |
| Automotive Body Control Module | IoT Edge Node Wake-Up Circuit |
Use Scenario: Driving LED status indicators from 12 V system MCU I/O via 3.3 V LDO domain. IC Role / Device Role / Timing Role: Non-inverting buffer isolating MCU GPIO from LED sink current path while maintaining logic polarity. Use Value: Prevents MCU port latch-up during LED short-circuit events and ensures consistent turn-on timing across temperature. | Use Scenario: Conditioning wake-up signals from passive infrared (PIR) motion sensors to ultra-low-power microcontroller interrupt inputs. IC Role / Device Role / Timing Role: Schmitt-trigger buffer converting slow-rising PIR output into clean, jitter-free digital edge for wake-up detection. Use Value: Reduces false wake-ups by >99% compared to direct MCU input, extending deep-sleep duration in battery-operated nodes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual non-inverting buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G34DBVR | Higher IOH/IOL (±24 mA), wider VCC range (1.65–5.5 V), no input hysteresis | Better for driving heavier loads but unsuitable for noisy low-slew-rate inputs | Choose when higher drive strength is needed and input signal edges are fast and clean |
| 74AHC2G34GW,125 | Higher VCC min (2.0 V), faster tPD (1.7 ns), no IOFF or hysteresis | Optimized for speed in 3.3 V/5 V systems; lacks ultra-low-VCC support and power-down isolation | Prefer for high-speed clock distribution where 0.8 V operation and IOFF are not required |
Compared with SN74LVC2G34DBVR and 74AHC2G34GW,125, the 74AUP2G34GF,132 uniquely combines sub-1 µA quiescent current, 0.8 V minimum supply, and Schmitt-trigger inputs-making it the only option for battery-powered, noise-prone, mixed-voltage sensor interfaces requiring long-term reliability.
Availability
74AUP2G34GF,132 is available at Aetrix Electronics and suitable for industrial sensor interface, portable medical device logic, and automotive body control modules requiring stable component supply across extended temperature and low-power constraints.
Supply support for 74AUP2G34GF,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, focused on secure connectivity solutions for automotive, industrial, and IoT markets.
The 74AUP series targets ultra-low-power logic applications in battery-constrained and thermally demanding environments, emphasizing energy efficiency, wide supply flexibility, and robust signal integrity without external components.
FAQ
Is the 74AUP2G34GF,132 compatible with 1.2 V logic systems?
Yes. The device is fully specified from 0.8 V to 3.6 V, and functional testing confirms reliable operation at 1.2 V with propagation delay ≤5.8 ns and output drive ≥±2.1 mA. Input thresholds scale with VCC, ensuring correct logic interpretation across the entire voltage range.
Does this IC support hot insertion or live board swapping?
Yes. Its IOFF feature forces outputs into high-impedance state when VCC = 0 V, preventing current backflow into powered circuitry. This allows safe insertion into live backplanes or modular systems without risk of latch-up or bus contention.
Can the 74AUP2G34GF,132 replace a 74LVC2G34 in an existing design?
Only if supply voltage remains ≥1.65 V and input signal slew rates exceed 0.1 V/ns. The AUP variant adds hysteresis and lower VCC capability but has reduced drive strength. Layout changes may be needed due to different XSON6 thermal pad requirements and decoupling placement.
What is the maximum capacitive load this buffer can drive reliably?
The device is characterized up to 50 pF load capacitance at 3.3 V with tPD ≤2.5 ns and overshoot <10% of VCC. For loads >30 pF, add a series resistor (22–47 Ω) near the output to suppress ringing without degrading edge rate below system timing margins.
74AUP2G34GF,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT891 (1x1)
74AUP2G34GF,132 FAQ
1.How can I place an order for 74AUP2G34GF,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G34GF,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G34GF,132 reliable?
The price and inventory of 74AUP2G34GF,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G34GF,132 is usually 5 days.
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5.How can I obtain technical support or documentation for 74AUP2G34GF,132?
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6.How does Aetrix verify that 74AUP2G34GF,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G34GF,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G34GF,132 meets industry standards.
7.What is the process for return or replacement of 74AUP2G34GF,132?
All 74AUP2G34GF,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G34GF,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G34GF,132 part is unused and in its original packaging.
Return procedure for 74AUP2G34GF,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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