Nexperia USA Inc. 74AUP2G34GM,132
- Part No.:
- 74AUP2G34GM,132
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP2G34GM,132.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:1,405
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AUP2G34GM,132 from Nexperia is a dual CMOS buffer with Schmitt-trigger inputs, designed for low-power signal conditioning in space-constrained digital systems. It operates across 0.8 V to 3.6 V supply, delivers ≤1.4 μA max ICC at −40 °C to +125 °C, features IOFF partial power-down protection, and supports ≤4.2 ns propagation delay (VCC = 3.0 V, CL = 5 pF). It is used in battery-powered sensor interfaces and I²C bus level-shifting circuits.
For engineers reviewing the 74AUP2G34GM,132 datasheet, 74AUP2G34GM,132 pinout, 74AUP2G34GM,132 application, or 74AUP2G34GM,132 equivalent, this device serves as a rail-to-rail compatible dual buffer where ultra-low static current, input overvoltage tolerance to 3.6 V, and guaranteed operation down to 0.8 V are critical selection criteria.
Technical Context
The 74AUP2G34GM,132 implements two independent non-inverting buffers, each with Schmitt-trigger input thresholds that tolerate slow-rising signals and reject noise. Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V.
It complies with JEDEC standards JESD8-12 through JESD8C across five voltage bands and meets HBM ESD >5000 V and CDM >1000 V. The device is characterized from −40 °C to +125 °C and supports dynamic loading up to 30 pF.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage range | 0.8 V to 3.6 V - enables direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains |
| Max ICC (−40 °C to +125 °C) | 1.4 μA - ensures <1 μW static power at 1.8 V, critical for always-on IoT nodes |
| Propagation delay (VCC = 3.0 V, CL = 5 pF) | 4.2 ns max - supports >100 MHz toggle rates in clean signal paths |
| IOFF leakage (VCC = 0 V) | ±0.75 μA - prevents cross-coupling and backfeed in multi-rail partial-power-down systems |
| Input overvoltage tolerance | 3.6 V - allows safe interfacing with higher-voltage peripherals without external clamping |
| Operating temperature | −40 °C to +125 °C - qualified for under-hood automotive modules and industrial control cabinets |
| ESD robustness (HBM) | >5000 V - reduces need for external ESD protection in handheld and field-deployed equipment |
Pinout & Package
XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 × 1.45 × 0.5 mm; thermal pad not present; moisture sensitivity level MSL3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1A - Input A of Buffer 1 | Accepts Schmitt-triggered logic signal; VIH/VIL thresholds scale with VCC |
| 2 | GND - Ground reference | Primary return path for both buffers and internal bias networks; must be low-impedance |
| 3 | 2A - Input A of Buffer 2 | Independent input with identical Schmitt characteristics to Pin 1 |
| 4 | 2Y - Output Y of Buffer 2 | CMOS push-pull output; sinks/sourcing up to ±20 mA; IOFF active when VCC = 0 V |
| 5 | VCC - Supply voltage | Single supply input; powers both buffers and IOFF circuitry; decoupling required within 2 mm |
| 6 | 1Y - Output Y of Buffer 1 | Electrically isolated from 2Y; same drive strength and IOFF behavior as Pin 4 |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Hysteresis ≥0.3×VCC ensures reliable switching on noisy or slow-rising signals (e.g., mechanical switch debouncing) |
| IOFF partial power-down | Output disable at VCC = 0 V limits back-current to ±0.75 μA, enabling hot-swap and multi-voltage domain isolation |
| Ultra-low ICC | 1.4 μA max at +125 °C enables >10-year battery life in coin-cell–powered wake-up circuits |
| Overvoltage-tolerant inputs | Withstands 3.6 V input regardless of VCC (down to 0.8 V), eliminating level translators in mixed-supply systems |
| Wide temperature range | Specified from −40 °C to +125 °C supports deployment in automotive engine control units and industrial PLCs |
Applications
| Industrial Sensor Interface | I²C Bus Level Translation |
|---|---|
|
Use Scenario: Isolating analog sensor outputs before ADC sampling in a 1.8 V microcontroller system with shared 3.3 V supply rails. IC Role / Device Role / Timing Role: Dual buffer conditions slow-rising thermistor or potentiometer signals while rejecting EMI-induced glitches via Schmitt action. Use Value: Eliminates external RC filters and discrete transistors; maintains signal integrity without adding propagation delay beyond 4.2 ns. |
Use Scenario: Bidirectional voltage translation between a 3.3 V master and 1.8 V slave on an I²C bus with pull-ups to separate supplies. IC Role / Device Role / Timing Role: Acts as passive, direction-agnostic level shifter using its overvoltage-tolerant inputs and rail-compatible outputs. Use Value: No external biasing or enable control needed; supports standard I²C timing with <4.2 ns added delay per transition. |
| Low-Power Wearable Controller | Automotive Body Control Module |
|
Use Scenario: Driving LED indicators and button inputs in a Bluetooth earbud with intermittent 0.9 V supply from a buck-boost converter. IC Role / Device Role / Timing Role: Buffers wake-up interrupt signals and status flags while consuming <1.4 μA during sleep mode. Use Value: Enables full system shutdown with zero leakage path; IOFF prevents current backflow into powered-down subsystems. |
Use Scenario: Signal conditioning for door lock actuator feedback and ambient light sensor inputs in a BCM operating at 125 °C ambient. IC Role / Device Role / Timing Role: Provides noise-immune buffering for slow-switching mechanical sensors and analog front-end references. Use Value: Guaranteed operation at full spec over −40 °C to +125 °C avoids derating or thermal margin loss in under-dash locations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC2G34GM,132 | Higher ICC (max 4 μA at +125 °C); no IOFF; VCC min = 1.65 V | Lacks partial power-down capability; unsuitable for multi-rail hot-swap systems | Select only if supply is stable ≥1.65 V and IOFF is unnecessary |
| SN74AUP2G34DSFR | Same AUP family specs but in USON-6 (SOT-1115); 0.9 × 1.0 × 0.35 mm body | Smaller footprint and lower thermal mass; identical electrical performance | Prefer for ultra-dense PCB layouts where 0.1 mm height reduction matters |
Compared with 74LVC2G34GM,132, the 74AUP2G34GM,132 provides 3× lower static current and IOFF protection; versus SN74AUP2G34DSFR, it trades 0.1 mm height for improved thermal dissipation in XSON6 (SOT886) packaging.
Availability
74AUP2G34GM,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, battery-powered wearables, automotive body control modules, and I²C level translation requiring stable component supply across extended temperature ranges.
Supply support for 74AUP2G34GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading semiconductor manufacturer specializing in high-performance, energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer markets.
The 74AUP (Advanced Ultra-low Power) product line targets ultra-low-power digital signal conditioning in space- and energy-constrained applications such as portable medical devices and smart sensors.
FAQ
Does the 74AUP2G34GM,132 support true bidirectional signal translation?
No. It is a unidirectional dual buffer with independent inputs and outputs. While its overvoltage-tolerant inputs allow use in passive I²C level-shifting configurations, it lacks automatic direction sensing or bus arbitration logic. External pull-up resistors and proper voltage domain separation are required for correct bidirectional operation.
What is the maximum capacitive load the 74AUP2G34GM,132 can drive reliably?
The device is fully characterized up to 30 pF load capacitance, with propagation delay increasing from 4.2 ns (CL = 5 pF) to 7.2 ns (CL = 30 pF) at VCC = 3.0 V. Driving >30 pF may cause excessive rise/fall times or output overshoot; for heavier loads, add series termination or consider a driver with higher output current.
Can the 74AUP2G34GM,132 be operated with VCC = 0.7 V?
No. The absolute minimum recommended VCC is 0.8 V per Table 6. Operation below 0.8 V risks undefined logic states, increased propagation delay variability, and failure to meet VIH/VIL thresholds. The device is not characterized or guaranteed below this voltage.
How does the IOFF feature behave when VCC ramps from 0 V to nominal?
IOFF remains active until VCC exceeds ~0.2 V; output impedance stays >100 MΩ during ramp-up. Once VCC reaches operational threshold (~0.8 V), outputs transition to normal CMOS drive within one propagation delay cycle. No external enable signal is required - IOFF is fully automatic and internal.
74AUP2G34GM,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT886 (1.45x1)
74AUP2G34GM,132 FAQ
1.How can I place an order for 74AUP2G34GM,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G34GM,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G34GM,132 reliable?
The price and inventory of 74AUP2G34GM,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G34GM,132 is usually 5 days.
3.What payment methods are accepted for 74AUP2G34GM,132?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G34GM,132 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP2G34GM,132?
74AUP2G34GM,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G34GM,132 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G34GM,132?
For technical support, including 74AUP2G34GM,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G34GM,132 requirements.
6.How does Aetrix verify that 74AUP2G34GM,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G34GM,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G34GM,132 meets industry standards.
7.What is the process for return or replacement of 74AUP2G34GM,132?
All 74AUP2G34GM,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G34GM,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G34GM,132 part is unused and in its original packaging.
Return procedure for 74AUP2G34GM,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP2G34GM,132 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

