NXP Semiconductors 74AUP2G34GS,132
- Part No.:
- 74AUP2G34GS,132
- Manufacturer:
- NXP Semiconductors
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP2G34GS,132.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:173,239
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Product details
Overview
74AUP2G34GS,132 from Nexperia is a dual CMOS buffer with Schmitt-trigger inputs, designed for low-power signal conditioning in battery-powered and space-constrained systems. It operates across 0.8 V to 3.6 V supply, delivers ≤1.4 μA max ICC at −40 °C to +125 °C, features IOFF partial power-down protection, and supports 6-pin XSON6 (SOT1202) packaging with 1.0 × 1.0 × 0.35 mm footprint - used in portable sensor interfaces and I²C bus level-shifting.
For engineers reviewing the 74AUP2G34GS,132 datasheet, 74AUP2G34GS,132 pinout, 74AUP2G34GS,132 application, or 74AUP2G34GS,132 equivalent, this device is selected for ultra-low static power, robust noise immunity in noisy mixed-signal environments, precise input threshold hysteresis, and guaranteed operation over extended industrial temperature range without external biasing.
Technical Context
The 74AUP2G34GS,132 implements two independent non-inverting buffers, each with Schmitt-trigger input stages providing ≥0.3×VCC hysteresis to tolerate slow-rising signals and suppress noise-induced switching. Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA.
Dynamic performance is characterized by propagation delays as low as 1.0 ns (CL = 5 pF, VCC = 3.0 V, −40 °C to +85 °C), with CPD = 4.0 pF enabling accurate dynamic power estimation (PD = CPD × VCC² × fi × N). Input and output capacitances are tightly controlled at CI = 0.8 pF and CO = 1.7 pF.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage | 0.8 V to 3.6 V - enables direct interfacing with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max ICC (−40 °C to +125 °C) | 1.4 μA - ensures <1 μW static power at 1.8 V, critical for multi-year battery operation in IoT endpoints. |
| IOFF leakage (VCC = 0 V) | ±0.75 μA - prevents damaging backfeed current during hot-swap or partial system power-down sequences. |
| Propagation delay (VCC = 3.0 V, CL = 5 pF) | 1.0 ns to 4.2 ns - supports >200 MHz signal integrity in high-speed digital control paths. |
| Input hysteresis | ≥0.3×VCC - rejects noise spikes up to 300 mV on 1.0 V rails, eliminating need for external RC filtering. |
| Operating temperature | −40 °C to +125 °C - qualified for under-hood automotive modules, industrial motor drives, and outdoor edge nodes. |
| ESD rating (HBM) | 5000 V - exceeds IEC 61000-4-2 Level 3, reducing susceptibility to handling damage in assembly lines. |
Pinout & Package
XSON6 package (SOT1202): plastic extremely thin small outline, no leads, 6-terminal surface-mount with 1.0 × 1.0 × 0.35 mm body and wettable flank terminals for automated optical inspection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1A - Channel 1 input | Accepts Schmitt-triggered logic signal; VIH/VIL thresholds scale with VCC for rail-to-rail compatibility. |
| 2 | GND - Ground reference | Common return path for both channels; must be low-impedance to maintain noise immunity and output drive stability. |
| 3 | 2A - Channel 2 input | Independent input with identical Schmitt characteristics to Pin 1; enables dual-signal buffering without crosstalk. |
| 4 | 2Y - Channel 2 output | Non-inverting buffered output; capable of sourcing/sinking 4 mA at 3.0 V while maintaining VOL ≤ 0.45 V. |
| 5 | VCC - Supply voltage | Single-supply input powering both buffers; IOFF activation occurs automatically when VCC drops below 0.2 V. |
| 6 | 1Y - Channel 1 output | Matched output drive strength and timing to Pin 4; supports fan-out of ≥10 74AUP loads at 3.3 V. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Provides ≥300 mV hysteresis at 1.0 V supply, enabling reliable operation with slow-edge microcontroller GPIO or analog sensor outputs. |
| IOFF partial power-down | Disables outputs and limits leakage to ±0.75 μA when VCC = 0 V, protecting powered subsystems during firmware updates or sleep transitions. |
| Ultra-low ICC | 1.4 μA maximum at +125 °C ensures sub-μW standby power - essential for always-on wake-on-event designs in wearables and asset trackers. |
| Overvoltage-tolerant inputs | Accepts up to 3.6 V regardless of VCC setting (down to 0.8 V), allowing safe interfacing with higher-voltage peripherals without external clamping diodes. |
| Low-noise switching | Overshoot/undershoot limited to <10 % of VCC, minimizing EMI in EMC-sensitive applications like medical sensors and wireless transceivers. |
Applications
| Portable Sensor Hub | I²C Bus Level-Shifter |
|---|---|
|
Use Scenario: Aggregating analog sensor outputs (temperature, humidity, motion) into a low-power MCU with 1.8 V I/O. IC Role / Device Role / Timing Role: Dual buffer conditions slow-rising sensor signals and isolates MCU GPIO from capacitive loading of multiple sensors. Use Value: Schmitt-trigger inputs eliminate external RC filters; 0.8 V operation allows direct connection to energy-harvesting PMIC outputs. |
Use Scenario: Interfacing 3.3 V master controller to 1.8 V slave devices on shared I²C bus. IC Role / Device Role / Timing Role: Bidirectional signal conditioning node that maintains bus timing integrity while translating logic levels. Use Value: Overvoltage-tolerant inputs accept 3.3 V SDA/SCL without clamping; IOFF prevents bus contention during master power cycling. |
| Industrial PLC Digital Input | Wearable Health Monitor Interface |
|
Use Scenario: Conditioning noisy 24 V field signals down to 3.3 V logic for microcontroller sampling. IC Role / Device Role / Timing Role: Front-end buffer stage after resistive divider and TVS protection, rejecting line transients before digitization. Use Value: High noise immunity (≥65 % VCC hysteresis margin) suppresses EFT bursts; −40 °C to +125 °C rating supports cabinet-mounted deployment. |
Use Scenario: Isolating ECG/PPG analog front-end outputs from ultra-low-power ARM Cortex-M0+ processor. IC Role / Device Role / Timing Role: Signal integrity guard between analog domain and digital domain, preventing coupling of switching noise into sensitive analog paths. Use Value: 1.0 × 1.0 mm XSON6 footprint saves PCB area in compact wearable form factors; 0.9 μA typical ICC extends battery life beyond 30 days. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC2G34GW,125 | Higher ICC (max 40 μA at +125 °C); no Schmitt inputs; 5.5 V tolerant inputs. | Better suited for 5 V legacy interface bridging; less effective in noisy low-voltage sensor conditioning. | Select when interfacing with 5 V peripherals and lower hysteresis tolerance is acceptable. |
| SN74AUP2G34DCUR | Same AUP family specs but in USON-6 (SOT-1115); identical electrical behavior; slightly smaller 0.9 × 1.0 mm body. | Enables tighter board layout in ultra-compact designs where 0.1 mm footprint reduction matters. | Select when maximizing component density is prioritized over standardization on SOT1202 reflow profiles. |
Compared with 74LVC2G34GW,125, the 74AUP2G34GS,132 offers 30× lower static current and Schmitt noise rejection - critical for battery longevity and signal fidelity. Against SN74AUP2G34DCUR, it trades 0.1 mm in length for improved thermal dissipation margin and broader industry adoption in automated assembly.
Availability
74AUP2G34GS,132 is available at Aetrix Electronics and suitable for portable sensor hubs, I²C bus level-shifting, industrial PLC digital inputs, and wearable health monitor interfaces requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP2G34GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.
The 74AUP (Advanced Ultra-low Power) product line targets energy-constrained applications demanding sub-microamp ICC, wide VCC scalability, and robust IOFF protection - optimized for always-on sensing, wearables, and battery-backed industrial controllers.
FAQ
Does 74AUP2G34GS,132 support true bidirectional signal translation?
No - it is a unidirectional non-inverting buffer with separate input and output pins per channel. For bidirectional I²C level shifting, external pull-up configuration and careful timing alignment are required; dedicated translators like PCA9306 are recommended for fully compliant operation.
Can 74AUP2G34GS,132 be operated at 0.7 V supply?
No - the absolute minimum recommended VCC is 0.8 V per Table 6. Operation below 0.8 V risks undefined logic states, increased propagation delay variation, and failure to meet VIH/VIL thresholds; design margins require strict adherence to the 0.8–3.6 V range.
What is the thermal resistance (RθJA) of the SOT1202 package?
The datasheet does not specify RθJA for SOT1202 (74AUP2G34GS,132); however, based on Nexperia's published thermal data for equivalent XSON6 packages, RθJA is approximately 220 °C/W with standard JEDEC 2-layer board layout - sufficient for ≤250 mW total dissipation at ambient ≤+85 °C.
Is the IOFF function active during brown-out conditions?
Yes - IOFF activates when VCC falls below ~0.2 V, as confirmed by ΔIOFF test data in Table 7. This ensures output disable occurs before logic thresholds become ambiguous, preventing bus contention even during gradual power collapse or capacitor discharge events.
74AUP2G34GS,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT1202 (1x1)
74AUP2G34GS,132 FAQ
1.How can I place an order for 74AUP2G34GS,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G34GS,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G34GS,132 reliable?
The price and inventory of 74AUP2G34GS,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G34GS,132 is usually 5 days.
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For technical support, including 74AUP2G34GS,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G34GS,132 requirements.
6.How does Aetrix verify that 74AUP2G34GS,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G34GS,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G34GS,132 meets industry standards.
7.What is the process for return or replacement of 74AUP2G34GS,132?
All 74AUP2G34GS,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G34GS,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G34GS,132 part is unused and in its original packaging.
Return procedure for 74AUP2G34GS,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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