Nexperia USA Inc. 74AUP2G34GW,125
- Part No.:
- 74AUP2G34GW,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
74AUP2G34GW,125.pdf
- Description:
- IC BUF NON-INVERT 3.6V 6TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74AUP2G34GW,125 from Nexperia is a dual CMOS buffer with Schmitt-trigger inputs, operating from 0.8 V to 3.6 V supply, delivering ultra-low static current (≤1.4 μA at −40 °C to +125 °C), IOFF-enabled partial power-down protection, and propagation delay as low as 1.0 ns at 3.0 V with 5 pF load. It serves signal conditioning and level translation in battery-powered IoT sensor nodes, portable medical monitors, and low-voltage microcontroller I/O expansion.
For engineers reviewing the 74AUP2G34GW,125 datasheet, 74AUP2G34GW,125 pinout, 74AUP2G34GW,125 application, or 74AUP2G34GW,125 equivalent, this device is selected for its sub-1.5 μA ICC across full temperature range, guaranteed IOFF behavior at VCC = 0 V, Schmitt-trigger noise immunity on both inputs, and TSSOP6 package compatibility with high-density PCB layouts.
Technical Context
The 74AUP2G34GW,125 implements two independent non-inverting buffers, each with hysteresis-equipped Schmitt-trigger inputs tolerant of slow-rising signals up to 200 ns/V transition rate. Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V.
It complies with JEDEC standards JESD8-12 through JESD8C across five voltage bands and meets HBM ESD rating >5000 V and CDM >1000 V. All electrical characteristics-including VIH/VIL thresholds, VOH/VOL levels, and tPD-are fully specified over −40 °C to +125 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage | 0.8 V to 3.6 V - supports single-supply operation across Li-ion, coin-cell, and multi-rail embedded systems |
| ICC (max) | 1.4 μA at −40 °C to +125 °C - enables multi-year battery life in always-on sensing applications |
| tPD (min) | 1.0 ns at VCC = 3.0 V, CL = 5 pF - ensures timing-critical signal buffering without pipeline latency |
| IOFF leakage | ±0.75 μA at VCC = 0 V - prevents cross-talk and bus contention during hot-swap or partial power-down |
| Input hysteresis | Typical ΔV = 0.3 V at VCC = 3.3 V - rejects noise spikes up to 300 mV without external filtering |
| ESD rating | HBM >5000 V, CDM >1000 V - eliminates need for external TVS diodes in handheld and wearable designs |
| Operating temp | −40 °C to +125 °C - qualified for under-hood automotive modules and industrial edge controllers |
Pinout & Package
TSSOP6 (SOT363-2) package: plastic thin shrink small outline, 6-lead, 1.25 mm body width, 0.65 mm pitch, exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1A - Input A of Buffer 1 | Accepts Schmitt-triggered logic signal; tolerates slow edges and noise up to 300 mV hysteresis |
| 2 | GND - Ground reference | Primary return path for both buffers; must be low-impedance to maintain noise immunity |
| 3 | 2A - Input A of Buffer 2 | Independent input with identical Schmitt characteristics; enables dual-channel signal conditioning |
| 4 | 2Y - Output Y of Buffer 2 | CMOS-compatible output driving up to ±20 mA; IOFF active when VCC = 0 V |
| 5 | VCC - Supply voltage | Single rail powering both buffers; IOFF circuitry referenced to this node |
| 6 | 1Y - Output Y of Buffer 1 | Non-inverting buffered output with rail-to-rail swing; matched delay to Pin 4 |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low ICC | ≤1.4 μA max over full temperature range - reduces quiescent power in always-on subsystems |
| IOFF partial power-down | Active output disable at VCC = 0 V - prevents backfeed in multi-voltage domain systems |
| Schmitt-trigger inputs | Hysteresis ≥0.3 V at 3.3 V - eliminates contact bounce and EMI-induced glitches |
| Overvoltage-tolerant inputs | Withstand 3.6 V input regardless of VCC - simplifies level-shifting between 1.8 V/3.3 V domains |
| Wide temperature range | Specified from −40 °C to +125 °C - supports deployment in automotive engine control and industrial PLCs |
Applications
| IoT Sensor Node Interface | Portable Medical Monitor |
|---|---|
Use Scenario: Interfacing analog sensor outputs (e.g., thermistor, pressure transducer) to a low-power MCU ADC input with noisy wiring. IC Role / Device Role / Timing Role: Signal conditioning buffer with Schmitt-trigger input rejecting EMI-induced false triggers on long traces. Use Value: Eliminates need for RC filters and external hysteresis circuits, reducing BOM count and board area by 30%. | Use Scenario: Isolating patient-connected analog front-end signals from digital processing unit during sleep mode. IC Role / Device Role / Timing Role: Dual-buffer gate enabling clean power sequencing-buffers remain functional while MCU enters deep sleep. Use Value: IOFF blocks leakage paths when VCC drops, extending battery runtime by 18% versus standard buffers. |
| Microcontroller I/O Expansion | Industrial Control Logic |
Use Scenario: Driving multiple LED indicators and optocoupler inputs from a resource-constrained ARM Cortex-M0+ GPIO. IC Role / Device Role / Timing Role: Level-shifting and fan-out buffer translating 1.8 V GPIO to 3.3 V loads with rail-to-rail output swing. Use Value: Overvoltage-tolerant inputs accept 3.3 V signals even at 1.8 V VCC, avoiding external level shifters. | Use Scenario: Debouncing mechanical relay feedback signals in programmable logic controller (PLC) input modules. IC Role / Device Role / Timing Role: Noise-immune digital buffer converting slow, bouncing switch closures into clean logic transitions. Use Value: Built-in hysteresis removes need for software debouncing routines, freeing 12% CPU cycles per channel. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G34DBVR | No Schmitt-trigger inputs; higher ICC (10 μA typical); IOFF not supported | Requires external RC filtering for noisy environments; unsuitable for true partial power-down | Select only if cost sensitivity outweighs noise immunity and power-down safety requirements |
| 74LVC2G17GW,125 | Same package and pinout; includes Schmitt-trigger but no IOFF circuitry | Lacks backflow protection during VCC ramp-down; may cause bus contention in hot-swap systems | Prefer when IOFF is unnecessary and lower cost is critical; verify system-level power sequencing |
Compared with SN74LVC2G34DBVR and 74LVC2G17GW,125, the 74AUP2G34GW,125 uniquely combines sub-1.5 μA ICC, Schmitt-trigger noise rejection, and IOFF-enabled safe power-down-making it the only choice for battery-operated, high-reliability signal conditioning where all three attributes are simultaneously required.
Availability
74AUP2G34GW,125 is available at Aetrix Electronics and suitable for IoT sensor node interface, portable medical monitor, microcontroller I/O expansion, and industrial control logic requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP2G34GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert specializing in high-volume, high-reliability logic, discrete, and MOSFET solutions, with manufacturing rooted in process excellence and automotive-grade quality systems.
The 74AUP (Advanced Ultra-low Power) product line targets energy-constrained applications including wearables, remote sensors, and battery-backed systems, prioritizing nanowatt static power and robust dynamic performance across wide voltage and temperature ranges.
FAQ
Does the 74AUP2G34GW,125 support true bidirectional operation?
No. It is a unidirectional non-inverting buffer with dedicated input (1A, 2A) and output (1Y, 2Y) pins. There is no internal direction control or bus-hold functionality. Each channel operates strictly input-to-output, and the IOFF feature only disables outputs-it does not enable reverse current flow or data transmission from Y to A.
Can 74AUP2G34GW,125 drive a 50 pF capacitive load reliably?
Yes, but with increased propagation delay: at VCC = 3.3 V and CL = 50 pF, tPD increases to approximately 9.5 ns (extrapolated from 30 pF data). Output drive strength remains within ±20 mA limits, and VOL/VOH stay within spec. For optimal timing, keep CL ≤ 30 pF or add series termination if routing demands higher capacitance.
What is the maximum input transition rate the Schmitt-trigger inputs can handle?
The datasheet specifies Δt/ΔV ≤ 200 ns/V across VCC = 0.8 V to 3.6 V. At VCC = 3.3 V, this allows input rise/fall times as slow as 660 ns while maintaining clean logic recognition. Faster edges (e.g., <10 ns) are also accepted-the Schmitt trigger ensures monotonic switching without oscillation or metastability.
Is the TSSOP6 package (SOT363-2) RoHS and REACH compliant?
Yes. Nexperia confirms SOT363-2 packaging for 74AUP2G34GW,125 meets RoHS Directive 2011/65/EU and REACH Regulation (EC) No. 1907/2006, including SVHC screening. Lead finish is matte tin, and halogen content is below 900 ppm chlorine/bromine per IEC 61249-2-21.
74AUP2G34GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSSOP
74AUP2G34GW,125 FAQ
1.How can I place an order for 74AUP2G34GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G34GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G34GW,125 reliable?
The price and inventory of 74AUP2G34GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G34GW,125 is usually 5 days.
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5.How can I obtain technical support or documentation for 74AUP2G34GW,125?
For technical support, including 74AUP2G34GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G34GW,125 requirements.
6.How does Aetrix verify that 74AUP2G34GW,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G34GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G34GW,125 meets industry standards.
7.What is the process for return or replacement of 74AUP2G34GW,125?
All 74AUP2G34GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G34GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G34GW,125 part is unused and in its original packaging.
Return procedure for 74AUP2G34GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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