NXP Semiconductors 74AUP2G38GT,115

Overview

74AUP2G38GT,115 from Nexperia is a low-power dual 2-input NAND gate with open-drain outputs, designed for level-shifting and wired-logic interfacing in battery-powered and space-constrained systems. It operates across 0.8 V to 3.6 V supply, features Schmitt-trigger inputs for noise immunity, supports partial power-down via IOFF, and is rated for −40 °C to +125 °C operation in XSON8 package.

For engineers reviewing the 74AUP2G38GT,115 datasheet, 74AUP2G38GT,115 pinout, 74AUP2G38GT,115 application, or 74AUP2G38GT,115 equivalent, this device is selected for ultra-low static current (≤1.4 μA), open-drain bus arbitration, I²C-compatible voltage translation, and robust ESD protection (HBM >5 kV) in compact logic interface designs.

Technical Context

This dual NAND gate implements two independent 2-input logic functions with open-drain outputs-enabling active-LOW wired-OR and active-HIGH wired-AND configurations when multiple outputs share a common pull-up. Each input incorporates Schmitt-trigger hysteresis, ensuring reliable switching even with slow-rising/falling signals across the full 0.8–3.6 V VCC range.

The IOFF circuit actively disables output leakage during partial power-down, limiting backflow current to ±0.75 μA at VCC = 0 V. Static power consumption remains below 1.4 μA over temperature, while propagation delay ranges from 0.8 ns (VCC = 3.3 V, CL = 5 pF) to 2.1 ns (VCC = 3.3 V, CL = 30 pF) per gate.

Key Specifications

Pinout & Package

XSON8 plastic extremely thin small outline package (SOT833-1); no leads; 8 terminals; body dimensions 1.0 mm × 1.95 mm × 0.5 mm; terminal pitch 0.5 mm; wettable flank profile for automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual open-drain NAND gate applications.

Compared with SN74LVC2G38DCUR and 74LVC2G00GM,132, the 74AUP2G38GT,115 uniquely balances ultra-low ICC (<1.4 μA), true open-drain flexibility, and −40 °C to +125 °C qualification in the smallest XSON8 variant-making it optimal for energy-critical, space-constrained, and mixed-voltage automotive/industrial nodes.

Availability

74AUP2G38GT,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, I²C bus expansion, and battery-powered remote nodes requiring stable component supply across extended temperature and low-power operating conditions.

Supply support for 74AUP2G38GT,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in automotive, industrial, and mobile applications.

The 74AUP (Advanced Ultra-low Power) product line targets ultra-low-power logic functions for battery-operated and thermally constrained systems, emphasizing sub-microwatt static consumption, wide VCC scalability, and robust IO architecture.

FAQ

Can 74AUP2G38GT,115 drive standard I²C bus capacitance?

Yes. With 20 mA sink capability per open-drain output and typical VOL ≤0.5 V at 4 mA (VCC = 3.0 V), it meets I²C Fast-mode (400 kbps) requirements up to 400 pF bus capacitance when paired with a 2.2 kΩ pull-up to 3.3 V. Propagation delay remains under 4.9 ns, preserving timing margins.

Does the IOFF feature work when VCC = 0 V and inputs are biased to 3.3 V?

Yes. The IOFF circuit actively disables output FETs when VCC = 0 V, limiting backflow current to ±0.75 μA even if inputs or outputs are pulled to 3.6 V. This is verified per JESD78B Class II latch-up testing and enables safe hot-plug operation in modular systems.

What is the maximum recommended load capacitance for 100 MHz toggle operation?

At VCC = 3.3 V and Tamb = 25 °C, CL ≤15 pF maintains tpd ≤7.5 ns and ensures stable 100 MHz toggling. For CL = 30 pF, tpd increases to 15.3 ns, limiting practical toggle rate to ~30 MHz. Layout parasitics must be minimized to avoid exceeding total effective CL.

How does Schmitt-trigger input hysteresis improve performance in noisy environments?

Schmitt-trigger inputs provide ≥120 mV hysteresis at 3.3 V, meaning a rising input must exceed VIH by ≥120 mV before switching, and a falling input must drop below VIL by ≥120 mV to switch back. This prevents oscillation on slow or noisy edges-critical for switch debouncing and long-trace sensor interfacing.