Nexperia USA Inc. 74AUP2G58DPJ

Overview

74AUP2G58DP from Nexperia is a dual configurable multiple-function logic gate with Schmitt-trigger inputs, enabling on-PCB selection of AND, OR, NAND, NOR, XOR, inverter, or buffer per gate via 3-bit configuration inputs. It operates across 0.8 V to 3.6 V, delivers ≤0.9 μA max ICC at 125 °C, supports partial power-down via IOFF, and targets low-power sensor interface, battery-powered I/O expansion, and mixed-voltage level-shifting applications.

For engineers reviewing the 74AUP2G58DP datasheet, 74AUP2G58DP pinout, 74AUP2G58DP application, or 74AUP2G58DP equivalent, this device offers field-configurable logic functionality without firmware, ultra-low static current for always-on subsystems, robust noise immunity via Schmitt-trigger inputs, and guaranteed operation from –40 °C to +125 °C in TSSOP10 packaging.

Technical Context

The 74AUP2G58DP implements two independent configurable gates, each accepting three control inputs (nA/nB/nC) to select one of nine logic functions per gate. Its Schmitt-trigger inputs provide hysteresis (VH = 0.07–1.31 V depending on VCC), enabling reliable signal conditioning of slow or noisy digital signals.

IOFF circuitry actively disables outputs during power-down (VCC = 0 V), limiting backflow current to ±0.75 μA, while input tolerance up to 3.6 V allows interfacing with higher-voltage domains even when VCC is as low as 0.8 V.

Key Specifications

Pinout & Package

TSSOP10 plastic thin shrink small outline package (SOT552-1), 10-lead, 3 mm body width, 0.5 mm pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with 74LVC2G58DP, the 74AUP2G58DP provides 11× lower static current and true 0.8 V operation; compared with SN74LVC1G57DBVR, it integrates two gates in one TSSOP10 package, reducing footprint by 35 % and interconnect complexity.

Availability

74AUP2G58DP is available at Aetrix Electronics and suitable for industrial sensor interfaces, battery-powered I/O expansion, and mixed-voltage level translation requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP2G58DP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components - including logic, discrete, and MOSFET devices - with manufacturing rooted in process expertise and high-volume reliability.

The 74AUP (Advanced Ultra-low Power) logic family is designed specifically for ultra-low-power, wide-VCC, and high-noise-immunity applications in portable, industrial, and automotive-edge electronics.

FAQ

What logic functions can be configured per gate on the 74AUP2G58DP?

Each gate supports nine configurations: 2-input NAND, 2-input AND with inverted input, 2-input NOR with inverted input, 2-input OR, 2-input XOR, buffer, inverter, 2-input NAND with both inputs inverted, and 2-input OR with both inputs inverted - selected via the 3-bit nA/nB/nC control inputs per gate as defined in Table 4 and Figures 4–10.

Does the 74AUP2G58DP require external pull-up or pull-down resistors on its configuration inputs?

No. All inputs - including configuration pins 1A/1B/1C and 2A/2B/2C - can be directly tied to VCC or GND without external resistors, as confirmed in Section 1 (General description) and validated by absolute maximum ratings allowing VI = –0.5 V to +4.6 V.

How does the IOFF feature behave when VCC is ramping or partially powered?

IOFF activates when VCC falls below ~0.2 V, limiting output leakage to ±0.75 μA. During VCC ramp-up, outputs remain in high-impedance until VCC exceeds the minimum functional threshold (~0.8 V), preventing glitching or contention - verified in Table 8 (IOFF and ΔIOFF specifications).

Can the 74AUP2G58DP drive a 50 pF load at 3.3 V while maintaining timing specs?

No. The datasheet specifies dynamic characteristics only up to CL = 30 pF (Table 9). At CL = 50 pF, propagation delay increases beyond the 7.4 ns max (VCC = 3.0–3.6 V) specified for 30 pF, and output drive strength (±4 mA) may not sustain clean edges - use external buffering or reduce trace capacitance for reliable operation.