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Nexperia USA Inc. 74AUP2G58GUX

Part No.:
74AUP2G58GUX
Manufacturer:
Nexperia USA Inc.
Category:
Gates and Inverters - Multi-Function, Configurable
Package:
10-XFQFN
Datasheet:
Aetrix74AUP2G58GUX.pdf
Description:
IC SCHMITT TRIGGER DUAL XQFN10
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:14,403

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Product details

Overview

74AUP2G58GUX from Nexperia is a dual configurable multiple-function logic gate with Schmitt-trigger inputs, enabling on-PCB reconfiguration of each gate as AND, OR, NAND, NOR, XOR, inverter, or buffer via 3-bit function select inputs. It operates from 0.8 V to 3.6 V, delivers ≤0.9 μA max ICC at 25 °C, supports partial power-down via IOFF, and is rated for −40 °C to +125 °C ambient operation - used in low-power sensor interface and battery-powered control logic.

For engineers reviewing the 74AUP2G58GUX datasheet, 74AUP2G58GUX pinout, 74AUP2G58GUX application, or 74AUP2G58GUX equivalent, this page provides verified functional configuration details, validated Schmitt-trigger thresholds (VT+ = 1.88 V, VT− = 0.88 V at VCC = 3.0 V), IOFF-enabled power-down behavior, propagation delay down to 1.6 ns (VCC = 3.0 V, CL = 5 pF), and package-specific pin mapping for XQFN10 (SOT1160-1).

Technical Context

The device implements two independent configurable gates, each accepting three function-select inputs (nA/nB/nC) to determine logic behavior per Table 4 and Table 5 - including XOR, buffered pass-through, and inverted outputs. All inputs tolerate up to 3.6 V regardless of VCC level, enabling mixed-voltage interfacing.

Its Schmitt-trigger inputs provide hysteresis (VH = 0.79–1.31 V at VCC = 3.0 V), ensuring noise immunity in noisy environments. The IOFF circuit actively disables outputs during VCC = 0 V, limiting backflow current to ±0.75 μA maximum across −40 °C to +125 °C.

Key Specifications

ParameterValue and Actual Design Meaning
Supply Voltage0.8 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters.
Max ICC (25 °C)0.9 μA - ensures ultra-low static power in always-on monitoring circuits and wake-up logic.
IOFF Leakage±0.75 μA max at VCC = 0 V - prevents damaging back-current when one supply rail is powered down in multi-rail systems.
Propagation Delay1.6 ns min (VCC = 3.0 V, CL = 5 pF) - supports high-speed reconfigurable glue logic in compact timing-critical paths.
Input Hysteresis0.79–1.31 V at VCC = 3.0 V - rejects >100 mV noise spikes on slow-rising signals from mechanical switches or sensors.
Operating Temp−40 °C to +125 °C - qualified for under-hood automotive modules, industrial PLC I/O, and extended-range IoT edge nodes.
ESD RatingHBM >5000 V, CDM >1000 V - withstands handling and board-level ESD events without protection diodes.

Pinout & Package

XQFN10 (SOT1160-1) package: 1.40 × 1.80 × 0.50 mm body, no leads, 10 exposed terminals, wettable flank profile for automated optical inspection.

Pin/TerminalCircuit RoleDesign Meaning
12ASecond gate data input A - tied to VCC/GND or driven externally to configure logic function.
22YSecond gate output - drives downstream logic or analog comparators with rail-to-rail swing.
3GNDDedicated ground reference - must be low-inductance connection to minimize switching noise coupling.
41YFirst gate output - electrically isolated from 2Y; supports dual independent logic paths.
52CSecond gate function-select input C - part of 3-bit code defining gate behavior per Table 4.
61AFirst gate data input A - accepts 0–3.6 V regardless of VCC, enabling voltage translation.
72BSecond gate data input B - used with 2A/2C to define operand and function selection simultaneously.
8VCCSingle supply rail - powers both gates and internal configuration logic; decoupling required within 2 mm.
91CFirst gate function-select input C - determines logic type (e.g., NAND vs XOR) for Gate 1 independently.
101BFirst gate data input B - Schmitt-triggered to reject noise; compatible with open-drain or push-pull sources.

Key Features

FeatureDesign Value
Dual independent configurable gatesEach gate uses separate 3-bit select lines (nA/nB/nC) - eliminates need for discrete gate arrays or CPLD in space-constrained designs.
Schmitt-trigger inputs with programmable hysteresisVT+ = 1.88 V / VT− = 0.88 V at VCC = 3.0 V - ensures clean transitions on slow or noisy sensor outputs without external RC filtering.
IOFF partial power-down modeOutput disabled and leakage limited to ±0.75 μA at VCC = 0 V - enables safe hot-swap and rail sequencing in multi-supply systems.
Wide VCC range with 3.6 V-tolerant inputsOperates from 0.8 V (ultra-low-power modes) to 3.6 V (legacy 3.3 V systems) - reduces BOM count across voltage-scaled platforms.
High noise immunity & low overshootOvershoot/undershoot <10% of VCC - minimizes EMI and crosstalk in dense PCB layouts with adjacent high-speed traces.

Applications

Industrial Sensor InterfaceLow-Power Wearable Control

Use Scenario: Interfacing mechanical limit switches and analog sensor outputs to microcontroller GPIOs in factory automation panels.

IC Role / Device Role / Timing Role: Configured as Schmitt-triggered inverters to debounce switch bounce and convert slow-rising thermistor signals into clean digital edges.

Use Value: Eliminates external RC networks and pull-up resistors; reduces component count by 4 parts per channel while maintaining >100 mV noise margin.

Use Scenario: Managing button press detection and LED driver enable logic in coin-cell-powered fitness trackers.

IC Role / Device Role / Timing Role: Dual gate configured as buffer + inverter to isolate MCU wake-up interrupt lines and drive status LEDs with polarity inversion.

Use Value: Draws only 0.9 μA static current at 1.8 V - extends battery life beyond 12 months without compromising responsiveness.

Automotive Body ControllerIoT Edge Node Signal Conditioning

Use Scenario: Level-shifting and signal conditioning between 5 V legacy sensors and 3.3 V CAN transceiver logic in door module ECUs.

IC Role / Device Role / Timing Role: First gate as NAND, second as OR - implements priority-based fault signaling with simultaneous input sampling.

Use Value: Tolerates 3.6 V inputs at 3.3 V VCC - avoids dedicated level translators; −40 °C to +125 °C rating matches under-dash thermal requirements.

Use Scenario: Pre-processing analog-to-digital converter (ADC) reference voltage stability flags and SPI bus activity indicators in smart metering hardware.

IC Role / Device Role / Timing Role: Configured as XOR gates to detect signal transitions and generate synchronous strobes for timestamping ADC conversions.

Use Value: Propagation delay ≤1.9 ns at 3.0 V enables sub-microsecond event capture - critical for time-of-use energy billing accuracy.

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Alternative PartTechnical DifferenceApplication DifferenceSelection Advice
SN74LVC2G58DCKRNo Schmitt-trigger inputs; standard CMOS thresholds; higher ICC (max 10 μA); no IOFF.Lacks noise immunity for unconditioned sensor inputs; unsuitable for partial power-down systems.Select only if operating in clean, high-speed digital-only environments with stable 1.65–5.5 V supplies.
74AUP2G17GW,125Dual Schmitt-trigger buffer only (no configurability); identical VCC range and IOFF; lower pin count (6-pin).Fixed function limits flexibility - requires additional gates for XOR/NAND logic; saves board area where only buffering is needed.Choose when Schmitt-triggering is required but logic reconfiguration adds unnecessary complexity or cost.

Compared with SN74LVC2G58DCKR and 74AUP2G17GW,125, the 74AUP2G58GUX uniquely combines reconfigurable logic, Schmitt-trigger noise rejection, and IOFF-enabled power sequencing - making it optimal for mixed-signal edge nodes where layout space, supply flexibility, and robustness are jointly constrained.

Availability

74AUP2G58GUX is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power wearable control, automotive body controllers, and IoT edge node signal conditioning requiring stable component supply across extended temperature ranges.

Supply support for 74AUP2G58GUX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume applications.

The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained systems requiring sub-μA static current, wide VCC scalability, and robust signal integrity - directly addressing design challenges in portable, automotive, and industrial edge electronics.

FAQ

What logic functions can be implemented using the 74AUP2G58GUX?

The 74AUP2G58GUX supports ten distinct logic configurations per gate: AND, OR, NAND, NOR, XOR, inverter, buffer, and three variants with inverted inputs (e.g., AND with inverted B input). Configuration is set by the 3-bit combination applied to pins nA/nB/nC, as defined in Table 4 and Table 5 of the datasheet - all selectable without external programming hardware.

How does the IOFF feature protect the device during partial power-down?

When VCC = 0 V, the IOFF circuitry disables both outputs (1Y and 2Y), limiting leakage current to ±0.75 μA maximum across −40 °C to +125 °C. This prevents backflow current from live signal lines into the unpowered IC, protecting against latch-up and ensuring safe rail sequencing in multi-voltage systems like USB-C PD adapters or modular PLC backplanes.

Can the 74AUP2G58GUX interface between 1.8 V and 3.3 V logic domains?

Yes - its inputs accept voltages up to 3.6 V independent of VCC level, allowing 3.3 V signals to safely drive the device when powered at 1.8 V. Outputs swing rail-to-rail (VOH ≥ 1.62 V, VOL ≤ 0.36 V at VCC = 1.8 V, IO = ±1.9 mA), meeting 1.8 V logic thresholds while eliminating external level translators in mixed-voltage sensor hubs.

What is the minimum propagation delay achievable with the 74AUP2G58GUX?

The minimum guaranteed propagation delay is 1.6 ns (tpd) under recommended conditions: VCC = 3.0 V, CL = 5 pF, Tamb = −40 °C to +85 °C. At 25 °C and same conditions, typical delay is 1.9 ns. This performance holds across the full 0.8–3.6 V supply range, enabling use in timing-critical reconfigurable glue logic without speed compromise.

74AUP2G58GUX Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
74AUP
Package/Case:
10-XFQFN
Packaging:
Tape & Reel (TR)
Product Status:
Active
Logic Type:
Configurable Multiple Function
Number of Circuits:
2
Number of Inputs:
3
Schmitt Trigger Input:
Yes
Output Type:
Single-Ended
Current - Output High, Low:
4mA, 4mA
Voltage - Supply:
0.8V ~ 3.6V
Operating Temperature:
-40°C ~ 125°C
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
10-XQFN (1.4x1.8)

74AUP2G58GUX FAQ

1.How can I place an order for 74AUP2G58GUX through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP2G58GUX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP2G58GUX reliable?

The price and inventory of 74AUP2G58GUX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G58GUX is usually 5 days.

3.What payment methods are accepted for 74AUP2G58GUX?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G58GUX transactions.

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74AUP2G58GUX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP2G58GUX order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP2G58GUX?

For technical support, including 74AUP2G58GUX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G58GUX requirements.

6.How does Aetrix verify that 74AUP2G58GUX is sourced from the original manufacturer or authorized distributors?

All 74AUP2G58GUX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G58GUX meets industry standards.

7.What is the process for return or replacement of 74AUP2G58GUX?

All 74AUP2G58GUX units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G58GUX, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP2G58GUX part is unused and in its original packaging.

Return procedure for 74AUP2G58GUX:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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