Nexperia USA Inc. 74AUP2G79DC,125

Overview

74AUP2G79DC from Nexperia is a low-power dual positive-edge-triggered D-type flip-flop in VSSOP8 (SOT765-1) package, operating across 0.8 V to 3.6 V supply. It transfers data from D inputs to Q outputs on LOW-to-HIGH clock transitions, features Schmitt-trigger inputs for noise immunity, IOFF circuitry for partial power-down protection, and guarantees ICC ≤ 0.9 μA max at full temperature range (–40 °C to +125 °C). It is used in battery-powered sensor interfaces and low-voltage logic synchronization.

For engineers reviewing the 74AUP2G79DC datasheet, 74AUP2G79DC pinout, 74AUP2G79DC application, or 74AUP2G79DC equivalent, key selection criteria include its ultra-low static current, wide VCC tolerance, guaranteed set-up/hold timing down to 0.8 V, and IOFF-enabled system-level power sequencing in mixed-voltage domains.

Technical Context

This device implements two independent edge-triggered D flip-flops with identical functional behavior: each samples nD on the rising edge of nCP and updates nQ synchronously. All inputs incorporate Schmitt-trigger action, enabling robust operation with slow-rising signals across the full 0.8 V–3.6 V VCC range.

The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA max, making it suitable for hot-swap and multi-rail power management. Propagation delay ranges from 0.9 ns (VCC = 3.0 V, CL = 5 pF) to 14.2 ns (VCC = 0.8 V, CL = 30 pF), with maximum operating frequency up to 510 MHz at 3.3 V.

Key Specifications

Pinout & Package

VSSOP8 plastic very thin shrink small outline package (SOT765-1); 8 leads; body width 2.3 mm; pin 1 indicator located below marking code in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual D-type flip-flop applications.

Compared with SN74LVC2G74DCUR and 74AUP2G74DC,125, the 74AUP2G79DC delivers superior power efficiency and true partial power-down capability-critical for battery longevity and rail sequencing integrity-but trades off reset flexibility and absolute drive strength.

Availability

74AUP2G79DC is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power wearables, automotive body control modules, and multi-rail FPGA I/O bridging requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP2G79DC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.

The 74AUP (Advanced Ultra-low Power) logic family targets energy-constrained applications where sub-1 μA static current, wide VCC operation, and robust IOFF behavior are essential for system-level power management.

FAQ

What is the minimum VCC required for guaranteed operation?

The 74AUP2G79DC is fully specified from 0.8 V to 3.6 V. At VCC = 0.8 V, it guarantees tsu = 15.9 ns and tpd ≤ 25.6 ns (CL = 10 pF), with VIH = 0.70 × VCC and VIL = 0.30 × VCC. Operation below 0.8 V is not characterized and may result in undefined timing or logic states.

Does the IOFF feature require external control or enable signals?

No. IOFF is fully automatic and requires no external signal. When VCC drops to 0 V, internal circuitry disables all outputs regardless of input state, limiting backflow current to ±0.75 μA max. This occurs inherently-no OE pin or configuration register is involved.

Can 74AUP2G79DC inputs safely accept 5 V signals?

No. Absolute maximum input voltage is +4.6 V, but recommended operating input voltage is limited to 0 V to 3.6 V. Inputs are overvoltage-tolerant only up to 3.6 V-not 5 V. Applying 5 V risks permanent damage and violates JEDEC JESD8-B compliance at 3.0–3.6 V operation.

How does Schmitt-trigger input action improve system reliability?

Schmitt-trigger inputs provide hysteresis (≥0.3 × VCC), allowing clean logic transitions even with slow-rising/falling signals (e.g., from RC-filtered sensors or long PCB traces). This prevents multiple toggling during signal slew and increases noise immunity by up to 400 mV in typical 1.8 V systems.