NXP Semiconductors 74AUP2G79GD,125

Overview

74AUP2G79GD,125 from Nexperia is a low-power dual positive-edge-triggered D-type flip-flop in an XSON8 (SOT996-2) package, operating across 0.8 V to 3.6 V supply. It transfers data from D inputs to Q outputs on the LOW-to-HIGH clock transition, features Schmitt-trigger inputs for noise immunity, and supports partial power-down via IOFF circuitry. It is used in battery-powered sensor interfaces and ultra-low-power microcontroller peripheral synchronization.

For engineers reviewing the 74AUP2G79GD,125 datasheet, 74AUP2G79GD,125 pinout, 74AUP2G79GD,125 application, or 74AUP2G79GD,125 equivalent, key selection criteria include its 0.9 μA max ICC at 25 °C, -40 °C to +125 °C temperature range, IOFF-enabled power-down behavior, and dual-channel edge-triggered storage with <1 ns set-up time at 3.3 V.

Technical Context

This device implements two independent D-type latches synchronized to the rising edge of separate clock inputs (1CP, 2CP), with each channel supporting independent data capture and output retention. Its Schmitt-trigger inputs ensure robust operation with slow-rising signals across the full 0.8–3.6 V VCC range, eliminating external hysteresis components.

The IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current during partial system power-down - a critical requirement in multi-rail portable systems. Static and dynamic power consumption are minimized through advanced AUP logic family design, achieving sub-1 μA ICC and 2.7 pF CPD at 3.3 V.

Key Specifications

Pinout & Package

XSON8 (SOT996-2) package: plastic extremely thin small outline, no leads, 8 terminals, body size 1.35 mm × 1.0 mm × 0.35 mm, wettable flank compatible.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual D-type flip-flop applications.

Compared with SN74AUP2G79DCUR and 74LVC2G74GT, the 74AUP2G79GD,125 delivers superior power efficiency below 1.2 V, guaranteed IOFF functionality for multi-rail safety, and XSON8 wettable flank compatibility for reliable automated optical inspection in miniaturized designs.

Availability

74AUP2G79GD,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, wearable health monitors, and smart energy meters requiring stable component supply across extended temperature ranges and ultra-low power budgets.

Supply support for 74AUP2G79GD,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, discrete, and MOSFET solutions with focus on automotive, industrial, and mobile markets.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-constrained and thermally sensitive applications, emphasizing sub-1 μA static current, wide VCC operability, and robust IOFF behavior for modern multi-domain power architectures.

FAQ

What is the minimum recommended VCC for reliable operation at -40 °C?

The device is fully specified down to 0.8 V across the full -40 °C to +125 °C range. At -40 °C and 0.8 V, VIH remains ≥0.25×VCC (≥200 mV) and VOL stays ≤0.11 V with 4 mA load, ensuring noise margins >150 mV. No derating is required below 0.8 V.

Does the IOFF feature require external biasing or control signals?

No. IOFF activates automatically when VCC drops to 0 V - no enable pin, no external resistor, and no timing delay. Output impedance exceeds 10 MΩ within 100 ns of VCC collapse, preventing back-current regardless of I/O voltage levels (0 V to 3.6 V).

Can 1CP and 2CP be tied together for single-clock dual-output operation?

Yes. The datasheet explicitly supports common clocking: pins 1CP and 2CP may be connected to the same source. Propagation delays (tpd) remain matched within ±0.3 ns across channels at 3.3 V, preserving skew-critical timing in dual-data-path applications.

Is the XSON8 (SOT996-2) package compatible with standard reflow profiles?

Yes. The SOT996-2 variant uses standard Pb-free reflow profile J-STD-020D, peak temperature 260 °C, with ramp rate ≤3 °C/s. Its 0.35 mm height and wettable flanks support automated optical inspection and high-yield solder joint formation in fine-pitch SMT lines.