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NXP Semiconductors 74AUP2G79GM,125
- Part No.:
- 74AUP2G79GM,125
- Manufacturer:
- NXP Semiconductors
- Category:
- Flip Flops
- Package:
- 8-XFQFN Exposed Pad
- Datasheet:
-
74AUP2G79GM,125.pdf
- Description:
- IC DUAL D-TYPE F-F 8-XQFN
- Quantity:
- Payment:
- Shipping:
Inventory:74,276
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Product details
Overview
74AUP2G79GM,125 from Nexperia is a low-power dual positive-edge-triggered D-type flip-flop in XSON8 (SOT902-2) package, operating across 0.8 V to 3.6 V supply. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and guaranteed operation from –40 °C to +125 °C. Used in voltage-level translation and clock-synchronized data latching in ultra-low-power portable and industrial control logic.
For engineers reviewing the 74AUP2G79GM,125 datasheet, 74AUP2G79GM,125 pinout, 74AUP2G79GM,125 application, or 74AUP2G79GM,125 equivalent, key selection criteria include supply voltage flexibility (0.8–3.6 V), sub-1 μA static ICC, IOFF-enabled system power sequencing, and dual-channel edge-triggered storage with <1 ns setup time at 3.3 V.
Technical Context
This device implements two independent D-type flip-flops, each transferring data from D to Q on the LOW-to-HIGH transition of its dedicated clock input (1CP/2CP). Input data must be stable for ≥0.6 ns (at VCC = 3.3 V) before the clock edge to ensure reliable state capture.
Schmitt-trigger inputs enable robust operation with slow-rising signals across the full 0.8–3.6 V VCC range, while the IOFF circuit disables outputs when VCC = 0 V, preventing backflow current during partial power-down - critical for multi-rail system interoperability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interfacing with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters |
| Max Static Supply Current | 1.4 μA at –40 °C to +125 °C - enables battery-powered applications with multi-year standby life |
| Propagation Delay (tpd) | 1.2 ns typical at VCC = 3.3 V, CL = 5 pF - delivers high-speed synchronization in compact timing-critical paths |
| IOFF Leakage Current | ±0.75 μA max at VCC = 0 V - ensures safe isolation during hot-swap or rail sequencing without external blocking components |
| Input Threshold Hysteresis | Integrated Schmitt trigger - eliminates false triggering from noisy or slow-rising clocks across all VCC levels |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood automotive, industrial PLC, and extended-range IoT edge nodes |
| ESD Robustness | HBM >5000 V, CDM >1000 V - reduces need for external ESD protection in space-constrained PCB layouts |
Pinout & Package
XSON8 package (SOT902-2): plastic extremely thin small outline, no leads, 8 terminals, body size 1.35 mm × 1.0 mm × 0.35 mm, wettable flank compatible.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 2D | Second D-type flip-flop data input - sampled on rising edge of 2CP |
| 2 | 1Q | First flip-flop non-inverted output - drives downstream logic or feedback paths |
| 3 | VCC | Primary power supply - decoupling capacitor placement directly adjacent is mandatory for noise suppression |
| 4 | 2CP | Second flip-flop clock input - accepts Schmitt-triggered edges; must meet minimum pulse width (0.6 ns @ 3.3 V) |
| 5 | 2Q | Second flip-flop non-inverted output - electrically isolated from 1Q; supports independent load driving |
| 6 | 1D | First D-type flip-flop data input - asynchronous relative to 2D; requires independent setup timing |
| 7 | 1CP | First flip-flop clock input - rising-edge sensitive; shares no internal timing dependency with 2CP |
| 8 | GND | Digital ground reference - must be connected to low-impedance ground plane to maintain signal integrity and ICC stability |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC ≤ 1.4 μA over full temperature range - eliminates thermal derating concerns in sealed enclosures |
| IOFF partial power-down | Outputs disabled at VCC = 0 V with <0.75 μA leakage - enables safe inter-rail communication during power sequencing |
| Wide-VCC Schmitt inputs | Valid operation from 0.8 V to 3.6 V with hysteresis - tolerates >200 ns/V input slew rates without oscillation |
| High noise immunity | Exceeds JEDEC JESD8-x standards across five voltage bands - reduces susceptibility to crosstalk in dense mixed-signal layouts |
| Small-footprint packaging | SOT902-2 (XSON8) footprint: 1.35 × 1.0 mm - saves >65% board area vs. SO8 while maintaining solder joint reliability |
Applications
| Industrial Sensor Interface | Low-Power Wearable Controller |
|---|---|
|
Use Scenario: Synchronizing analog sensor sampling pulses with microcontroller clock domains in battery-operated condition monitoring nodes. IC Role / Device Role / Timing Role: Dual D-flip-flop acts as a metastability-hardened synchronizer, capturing asynchronous wake-up triggers and ADC-ready signals before routing to MCU GPIOs. Use Value: Sub-1.4 μA ICC extends battery life beyond 5 years in sleep mode; IOFF prevents backfeed when MCU is powered down but sensor remains active. |
Use Scenario: Debouncing mechanical button inputs and latching gesture-detection interrupts in hearables with strict size and power constraints. IC Role / Device Role / Timing Role: Each flip-flop captures edge-triggered events from separate sensors (e.g., tap and double-tap), providing clean, glitch-free interrupt flags to the host SoC. Use Value: 1.35 × 1.0 mm XSON8 footprint fits within tight wearable PCB real estate; Schmitt inputs eliminate external RC filters. |
| Automotive Body Control Module | IoT Edge Node Data Buffering |
|
Use Scenario: Level-shifting and synchronizing LIN bus status signals into 3.3 V domain microcontrollers in door module ECUs. IC Role / Device Role / Timing Role: Provides voltage-tolerant input capture and clock-domain crossing between 12 V-derived logic and MCU core logic. Use Value: –40 °C to +125 °C qualification ensures reliability in under-dash environments; IOFF protects against reverse-current during ignition cycling. |
Use Scenario: Capturing timestamped sensor readings from multiple environmental sensors before batch transmission over LPWAN. IC Role / Device Role / Timing Role: Dual latch holds latest valid measurements until the MCU initiates readout, decoupling sensor acquisition from radio duty cycle. Use Value: 0.8 V operation allows direct interface with energy-harvesting PMUs; <1.2 ns tpd ensures precise alignment of buffered data edges. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G74DCUR | Higher ICC (max 10 μA), no IOFF, wider VCC (1.65–5.5 V), larger VSSOP8 package | Requires external power-gating for partial shutdown; less suitable for ultra-low-power always-on nodes | Select when 5 V compatibility or higher drive strength (24 mA) is required; avoid where IOFF or sub-2 μA ICC is mandatory |
| 74LVC2G79GW,125 | Same AUP family, identical pinout and IOFF, but rated only to +85 °C (not +125 °C) | Limited to commercial/industrial ambient conditions; not qualified for under-hood or extended-temperature deployments | Acceptable for cost-sensitive consumer designs with ambient <85 °C; reject for automotive or harsh-environment use |
Compared with SN74LVC2G74DCUR and 74LVC2G79GW,125, the 74AUP2G79GM,125 uniquely combines ultra-low ICC (<1.4 μA), full –40 °C to +125 °C operation, and IOFF in a 1.35 mm × 1.0 mm footprint - making it the only option for thermally constrained, long-life, multi-rail systems requiring guaranteed metastability resilience.
Availability
74AUP2G79GM,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power wearables, automotive body control modules, and IoT edge node buffering requiring stable component supply across extended temperature ranges and ultra-low quiescent current.
Supply support for 74AUP2G79GM,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, discrete, and MOSFET solutions with leadership in process technology and application-specific design.
The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and energy-sensitive applications demanding nanowatt static power, wide VCC scalability, and robust signal integrity - optimized for portable, automotive, and industrial edge devices.
FAQ
What is the maximum clock frequency supported by the 74AUP2G79GM,125 at 3.3 V?
At VCC = 3.3 V and CL = 5 pF, the 74AUP2G79GM,125 achieves a maximum clock frequency (fmax) of 550 MHz at 25 °C, derating to 510 MHz over –40 °C to +125 °C. This is measured with specified load and test conditions per Figure 7 in the datasheet; actual system performance depends on PCB layout, termination, and fanout.
Does the 74AUP2G79GM,125 support voltage-level translation between different logic families?
Yes - its inputs accept voltages up to 3.6 V regardless of VCC (down to 0.8 V), and outputs swing rail-to-rail. For example, with VCC = 1.8 V, it can safely accept 3.3 V inputs and drive 1.8 V loads, enabling bidirectional level translation without external components or direction control.
How does the IOFF feature behave during power sequencing?
When VCC drops to 0 V, the IOFF circuit actively disables both Q outputs, limiting leakage to ±0.75 μA even if input or output pins remain biased at up to 3.6 V. This prevents damaging backflow current through the device, allowing safe hot-plug operation and independent rail sequencing in multi-voltage systems.
Is the 74AUP2G79GM,125 pin-compatible with other 74AUP2Gxx dual flip-flops?
No - the 74AUP2G79GM,125 uses a specific pinout (1=2D, 2=1Q, 3=VCC, 4=2CP, 5=2Q, 6=1D, 7=1CP, 8=GND) defined for SOT902-2. Other dual flip-flops like 74AUP2G80 (D-type with inverted outputs) or 74AUP2G74 (set/reset DFF) have different pin assignments and functional behavior; direct substitution is not supported.
74AUP2G79GM,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 8-XFQFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Active
- Function:
- Standard
- Type:
- D-Type
- Output Type:
- Non-Inverted
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 309 MHz
- Max Propagation Delay @ V, Max CL:
- 5.8ns @ 3.3V, 30pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Iq):
- 500 nA
- Input Capacitance:
- 0.6 pF
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XQFN (1.6x1.6)
74AUP2G79GM,125 FAQ
1.How can I place an order for 74AUP2G79GM,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G79GM,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G79GM,125 reliable?
The price and inventory of 74AUP2G79GM,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G79GM,125 is usually 5 days.
3.What payment methods are accepted for 74AUP2G79GM,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G79GM,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP2G79GM,125?
74AUP2G79GM,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G79GM,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G79GM,125?
For technical support, including 74AUP2G79GM,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G79GM,125 requirements.
6.How does Aetrix verify that 74AUP2G79GM,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G79GM,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G79GM,125 meets industry standards.
7.What is the process for return or replacement of 74AUP2G79GM,125?
All 74AUP2G79GM,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G79GM,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G79GM,125 part is unused and in its original packaging.
Return procedure for 74AUP2G79GM,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP2G79GM,125 Tags
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SN74HC74DR
Texas Instruments
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SN74HC574DWR
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74LVC1G74DC,125
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SN74HCT574DWR
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