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Nexperia USA Inc. 74AUP2G79GN,115

Part No.:
74AUP2G79GN,115
Manufacturer:
Nexperia USA Inc.
Category:
Flip Flops
Package:
8-XFDFN
Datasheet:
Aetrix74AUP2G79GN,115.pdf
Description:
IC FF D-TYPE DUAL 1BIT 8XSON
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:85,650

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Product details

Overview

74AUP2G79GN,115 from Nexperia is a low-power dual positive-edge-triggered D-type flip-flop in an XSON8 package (1.2 × 1.0 × 0.35 mm, SOT1116), operating from 0.8 V to 3.6 V supply. It transfers data from inputs 1D/2D to outputs 1Q/2Q on the LOW-to-HIGH clock transition, features Schmitt-trigger inputs for noise immunity, and includes IOFF circuitry for partial power-down protection. It is specified for automotive-grade temperature range (−40 °C to +125 °C) and used in battery-powered sensor interfaces and low-voltage logic synchronization.

For engineers reviewing the 74AUP2G79GN,115 datasheet, 74AUP2G79GN,115 pinout, 74AUP2G79GN,115 application, or 74AUP2G79GN,115 equivalent, key selection criteria include its ultra-low ICC (≤1.4 μA max at −40 °C to +125 °C), 0.8 V minimum VCC support, IOFF-enabled power-gating capability, and dual-channel edge-triggered storage with independent clock inputs.

Technical Context

This device implements two independent D-type latches synchronized to rising edges of separate clock inputs (1CP, 2CP), each requiring stable data (1D/2D) one setup time (tsu ≤ 1.0 ns at VCC = 3.6 V) before the clock transition. Its Schmitt-trigger inputs tolerate slow signal edges across the full 0.8–3.6 V VCC range, enabling robust operation in noisy mixed-signal environments.

The IOFF circuit disables outputs when VCC = 0 V, blocking backflow current during partial power-down - critical for system-level power sequencing in portable and automotive electronics. Static power consumption remains below 1.4 μA across the full industrial temperature range, and propagation delay is as low as 0.9 ns (VCC = 3.0–3.6 V, CL = 5 pF).

Key Specifications

ParameterValue and Actual Design Meaning
VCC Range0.8 V to 3.6 V - supports direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters
ICC (max)1.4 μA at −40 °C to +125 °C - enables multi-year battery life in always-on sensor nodes
tsu / th1.0 ns / 0 ns at VCC = 3.6 V - minimal timing margin required for high-speed synchronous sampling
fmax510 MHz at VCC = 3.6 V, CL = 5 pF - suitable for clock-domain crossing in sub-GHz digital subsystems
IOFF Leakage±0.75 μA at VCC = 0 V - prevents destructive current flow during hot-swap or power-rail sequencing
Operating Temp−40 °C to +125 °C - qualified for under-hood automotive and industrial control applications
ESD RatingHBM >5000 V, CDM >1000 V - withstands handling and board-level ESD events without protection diodes

Pinout & Package

XSON8 package (SOT1116): extremely thin small outline, no leads, 8-terminal surface-mount with body dimensions 1.2 mm × 1.0 mm × 0.35 mm; pin 1 indicator located below marking code "pP" at lower-left corner.

Pin/TerminalCircuit RoleDesign Meaning
12DSecond D-type data input - sampled on rising edge of 2CP
21QFirst Q output - reflects state of 1D after 1CP rising edge
3VCCPositive supply rail - powers both flip-flop channels and internal bias networks
42CPSecond clock input - rising edge triggers transfer of 2D to 2Q
52QSecond Q output - reflects state of 2D after 2CP rising edge
61DFirst D-type data input - sampled on rising edge of 1CP
71CPFirst clock input - rising edge triggers transfer of 1D to 1Q
8GNDGround reference - return path for all internal currents and IOFF discharge paths

Key Features

FeatureDesign Value
Ultra-low static powerICC ≤ 1.4 μA over full temperature range - eliminates need for power gating in always-on logic
IOFF partial power-downOutputs disabled with VCC = 0 V; leakage < ±0.75 μA - enables safe multi-rail sequencing
Schmitt-trigger inputsInput hysteresis ≥ 0.3 V at VCC = 3.6 V - rejects noise on slow-rising clock/data lines
Wide VCC compatibilityOperates down to 0.8 V - interoperable with advanced low-voltage microcontrollers and sensors
High ESD robustnessHBM >5000 V, CDM >1000 V - reduces need for external ESD protection components

Applications

IoT Sensor Node TimingAutomotive Body Control Module

Use Scenario: Synchronizing asynchronous sensor interrupts (e.g., motion, temperature) to a low-power MCU clock domain while maintaining nanosecond-level timing integrity.

IC Role / Device Role / Timing Role: Dual-edge-triggered register capturing event flags prior to wake-up, with independent clocks enabling staggered sampling.

Use Value: Enables deterministic interrupt latency (<1 ns jitter) and eliminates metastability risk without external synchronizers.

Use Scenario: Isolating and debouncing switch inputs (door lock, window up/down) in 12 V vehicle systems using 3.3 V logic rails.

IC Role / Device Role / Timing Role: Input latch holding mechanical switch state until polled by CAN-connected MCU; IOFF protects during sleep mode.

Use Value: Reduces system-level current draw by 2.1 μA per channel vs. standard logic, extending battery reserve time.

Wearable Health MonitorIndustrial PLC I/O Expansion

Use Scenario: Capturing biopotential waveform edges (ECG R-peak, SpO₂ pulse) into ultra-low-power SoC with sub-1 V supply.

IC Role / Device Role / Timing Role: Level-shifting and edge-capturing front-end register interfacing analog comparators to digital processing core.

Use Value: Operates at 0.8 V VCC - matches SoC's lowest active voltage, eliminating intermediate regulators.

Use Scenario: Adding isolated, glitch-free digital inputs to modular PLC backplanes where field wiring introduces noise and ground shifts.

IC Role / Device Role / Timing Role: Noise-immune input conditioner with Schmitt-trigger inputs and independent clock domains per channel.

Use Value: Eliminates false triggering from EMI transients up to 100 MHz due to 0.3 V hysteresis and 200 ns/V input slew tolerance.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual D-type flip-flop applications.

Alternative PartTechnical DifferenceApplication DifferenceSelection Advice
SN74LVC2G74DCURHigher ICC (10 μA typ), no IOFF, VCC min = 1.65 VNot suitable for 0.8–1.2 V systems or partial power-down sequencesSelect when cost sensitivity outweighs ultra-low-power and multi-rail requirements
74LVC2G79GW,125Same package (XSON8), but no Schmitt inputs and higher tsu (2.5 ns)Limited noise immunity; requires cleaner clock/data signalsSelect only in controlled PCB environments with tight layout and filtering

Compared with SN74LVC2G74DCUR and 74LVC2G79GW,125, the 74AUP2G79GN,115 uniquely delivers sub-1 μA static current, 0.8 V operation, and IOFF - making it the only choice for energy-constrained, multi-voltage, or hot-swappable designs.

Availability

74AUP2G79GN,115 is available at Aetrix Electronics and suitable for battery-powered IoT sensors, automotive body electronics, wearable health monitors, and industrial PLC I/O expansion requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP2G79GN,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, discrete, and MOSFET solutions optimized for efficiency, miniaturization, and robustness in high-volume applications.

The 74AUP (Advanced Ultra-low Power) logic family targets ultra-low-power, wide-VCC digital interfacing - specifically engineered for energy-sensitive applications including wearables, automotive sensors, and always-on edge devices.

FAQ

What is the maximum clock frequency supported by the 74AUP2G79GN,115?

The 74AUP2G79GN,115 achieves up to 510 MHz maximum clock frequency at VCC = 3.6 V with 5 pF load, dropping to 300 MHz at −40 °C to +125 °C. Performance scales with supply voltage: 480 MHz at 3.0 V, 270 MHz at 1.8 V, and 120 MHz at 1.2 V - all verified per JEDEC test conditions in the official datasheet.

Does the 74AUP2G79GN,115 support true bidirectional I/O or bus-hold functionality?

No. The 74AUP2G79GN,115 is a unidirectional dual D-type flip-flop with dedicated inputs (1D/2D, 1CP/2CP) and outputs (1Q/2Q). It does not implement bus-hold, weak pull-up/down, or tri-state drivers. Outputs are push-pull CMOS with VOH ≥ 2.3 V and VOL ≤ 0.5 V at VCC = 3.0 V and IO = ±4 mA.

Can the 74AUP2G79GN,115 be used with 0.8 V microcontrollers without level translation?

Yes. The device is fully specified from 0.8 V to 3.6 V, with VIH as low as 0.25×VCC and VIL as high as 0.30×VCC at 0.8 V - ensuring reliable recognition of logic HIGH/LOW from 0.8 V-core MCUs. Output VOH/VOL remain rail-to-rail compliant across this range, enabling direct connection.

How does the IOFF feature behave during power sequencing when VCC ramps from 0 V to nominal?

IOFF activates when VCC falls below ~0.2 V, disabling outputs and limiting leakage to ±0.75 μA even if inputs/outputs are biased to 3.6 V. During ramp-up, outputs remain in high-impedance until VCC exceeds ~0.5 V, preventing bus contention. This behavior is characterized across −40 °C to +125 °C and documented in Table 7 (IOFF and ΔIOFF parameters).

74AUP2G79GN,115 Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
74AUP
Package/Case:
8-XFDFN
Packaging:
Bulk
Product Status:
Active
Function:
Standard
Type:
D-Type
Output Type:
Non-Inverted
Number of Elements:
2
Number of Bits per Element:
1
Clock Frequency:
309 MHz
Max Propagation Delay @ V, Max CL:
5.8ns @ 3.3V, 30pF
Trigger Type:
Positive Edge
Current - Output High, Low:
4mA, 4mA
Voltage - Supply:
0.8V ~ 3.6V
Current - Quiescent (Iq):
500 nA
Input Capacitance:
0.6 pF
Operating Temperature:
-40°C ~ 125°C (TA)
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
8-XSON (1.2x1)

74AUP2G79GN,115 FAQ

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Please submit a Request for Quotation (RFQ) for 74AUP2G79GN,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

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The price and inventory of 74AUP2G79GN,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G79GN,115 is usually 5 days.

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5.How can I obtain technical support or documentation for 74AUP2G79GN,115?

For technical support, including 74AUP2G79GN,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G79GN,115 requirements.

6.How does Aetrix verify that 74AUP2G79GN,115 is sourced from the original manufacturer or authorized distributors?

All 74AUP2G79GN,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G79GN,115 meets industry standards.

7.What is the process for return or replacement of 74AUP2G79GN,115?

All 74AUP2G79GN,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G79GN,115, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP2G79GN,115 part is unused and in its original packaging.

Return procedure for 74AUP2G79GN,115:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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