Nexperia USA Inc. 74AUP2G80DC,125

Overview

74AUP2G80DC from Nexperia is a low-power dual positive-edge-triggered D-type flip-flop in VSSOP8 (SOT765-1) package, operating across 0.8 V to 3.6 V supply. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and guaranteed operation from –40 °C to +125 °C. Used in battery-powered sensor interfaces and level-shifting clock domains where ultra-low static current (≤1.4 μA max) and sub-1 ns setup time are critical.

For engineers reviewing the 74AUP2G80DC datasheet, 74AUP2G80DC pinout, 74AUP2G80DC application, or 74AUP2G80DC equivalent, key selection criteria include its dual independent DFF architecture with separate clock inputs, IOFF-enabled isolation during system sleep states, wide-VCC compatibility down to 0.8 V, and validated timing performance up to 510 MHz at 3.3 V with 5 pF load.

Technical Context

This device implements two independent edge-triggered D-type latches sharing no internal logic-each has dedicated D, CP, and Q terminals. Clock-to-Q propagation delay is specified from 1.0 ns (3.0–3.6 V, CL = 5 pF) to 20.9 ns (0.8 V), with setup times as low as 0.2 ns (HIGH) and hold times down to –0.3 ns (3.0–3.6 V).

Schmitt-trigger inputs enable robust operation with slow-rising signals across the full 0.8–3.6 V range, while IOFF circuitry actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA. ESD protection meets HBM >5000 V and CDM >1000 V per JEDEC JS-001/JS-002.

Key Specifications

Pinout & Package

VSSOP8 plastic very thin shrink small outline package (SOT765-1); 8 leads; body width 2.3 mm; 0.5 mm pitch; exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual D-type flip-flop applications.

Compared with SN74LVC2G80DCTR and 74LVC2G74DC,125, the 74AUP2G80DC delivers 7× lower static current, integrated IOFF for zero-backflow power sequencing, and Schmitt-triggered inputs for ruggedized signal acquisition - making it optimal for energy-constrained, electrically noisy, or multi-rail embedded systems.

Availability

74AUP2G80DC is available at Aetrix Electronics and suitable for industrial sensor hubs, automotive body control modules, wearable health monitors, and smart home Zigbee coordinators requiring stable component supply across extended temperature ranges and ultra-low power budgets.

Supply support for 74AUP2G80DC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for power efficiency and reliability.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and thermally constrained applications, emphasizing sub-μA static current, wide-VCC operation, and robust ESD/EMI resilience without sacrificing speed.

FAQ

Does the 74AUP2G80DC support mixed-voltage operation between its inputs and VCC?

Yes - inputs tolerate voltages up to 3.6 V regardless of VCC level (0.8–3.6 V), enabling direct connection to higher-voltage peripherals without external clamping. This is explicitly guaranteed in Table 6 (VI input voltage) and reinforced by absolute maximum ratings (VI = –0.5 V to +4.6 V).

How does the IOFF feature behave when VCC ramps down during system shutdown?

IOFF activates automatically when VCC drops below ~0.2 V, disabling outputs and limiting leakage to ±0.75 μA. This prevents back-current from powered downstream circuits into the de-energized IC, protecting both the 74AUP2G80DC and connected devices during uncontrolled power sequencing.

Can both flip-flops operate at different clock frequencies simultaneously?

Yes - the 1CP and 2CP pins are fully independent. Each flip-flop samples its respective D input on its own clock's rising edge, with no internal coupling or shared timing constraints. This enables asynchronous domain bridging, such as synchronizing two independent sensor streams into a single processor.

What is the minimum recommended bypass capacitance for stable operation at 500 MHz?

A minimum 100 nF X7R ceramic capacitor placed within 2 mm of the VCC–GND pair is required. At 500 MHz fmax, high-frequency supply noise rejection depends critically on low-inductance layout; additional 1 nF capacitors near each VCC pin further reduce impedance above 100 MHz.