Nexperia USA Inc. 74AUP2G80DC-Q100H

Overview

74AUP2G80DC-Q100 from Nexperia is a dual positive-edge-triggered D-type flip-flop in VSSOP8 (SOT765-1) package, operating across 0.8 V to 3.6 V supply voltage with AEC-Q100 Grade 1 automotive qualification (−40 °C to +125 °C). It transfers data from D inputs to Q outputs on LOW-to-HIGH clock transitions, features Schmitt-trigger inputs for noise immunity, and includes IOFF circuitry for partial power-down protection. It is used in automotive body control modules for synchronizing sensor interface signals.

For engineers reviewing the 74AUP2G80DC-Q100 datasheet, 74AUP2G80DC-Q100 pinout, 74AUP2G80DC-Q100 application, or 74AUP2G80DC-Q100 equivalent, this device supports low-voltage logic interfacing in safety-critical automotive subsystems where static current ≤1.4 μA, propagation delay ≤6.1 ns (VCC = 3.3 V, CL = 15 pF), and IOFF-enabled power sequencing are required.

Technical Context

This IC implements two independent edge-triggered D flip-flops sharing no internal logic-each has dedicated clock (1CP/2CP), data (1D/2D), and output (1Q/2Q) terminals. Its Schmitt-trigger inputs ensure robust operation with slow-rising signals across the full 0.8 V–3.6 V VCC range, while the IOFF feature disables outputs during power-down to prevent backflow current when VCC = 0 V.

It complies with JEDEC standards JESD8-12 through JESD8-B for multi-voltage operation and meets AEC-Q100 Grade 1 requirements, including latch-up immunity >100 mA and ESD protection of HBM >5000 V and CDM >1000 V-enabling use in engine bay and ADAS domain controllers without external protection circuitry.

Key Specifications

Pinout & Package

VSSOP8 (SOT765-1) package: plastic very thin shrink small outline, 8 leads, 2.3 mm body width, 0.5 mm lead pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual D-type flip-flop applications.

Compared with SN74LVC2G74DCUR and 74LVC2G80DP,125, the 74AUP2G80DC-Q100 uniquely delivers AEC-Q100 Grade 1 qualification, IOFF-enabled power sequencing, and 1.4 μA max ICC at +125 °C-making it the sole choice for production automotive control units requiring zero-risk power management and long-term reliability.

Availability

74AUP2G80DC-Q100 is available at Aetrix Electronics and suitable for automotive body control units, ADAS sensor synchronization circuits, and engine control module I/O expansion requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for 74AUP2G80DC-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for automotive, industrial, and mobile markets.

The 74AUP (Advanced Ultra-low Power) logic family targets automotive and battery-powered applications demanding ultra-low static current, wide voltage operation, and robust noise immunity-designed specifically for signal integrity in harsh electrical environments.

FAQ

Does 74AUP2G80DC-Q100 support true bidirectional data flow?

No. It is a unidirectional D-type flip-flop: data flows only from D inputs to Q outputs on clock edges. There is no internal feedback path or tri-state control enabling reverse data transfer. Each channel operates independently as a synchronous register with no bus transceiver capability.

Can the 74AUP2G80DC-Q100 operate reliably at 0.8 V with 10 MHz clock frequency?

Yes. At VCC = 0.8 V, fmax reaches 50 MHz (CL = 5 pF) and 28 MHz (CL = 30 pF), providing ample margin for 10 MHz operation. The Schmitt-trigger inputs maintain valid logic thresholds down to 0.8 V, and propagation delay remains ≤20.9 ns-ensuring timing closure in ultra-low-voltage subsystems.

What is the maximum capacitive load the outputs can drive without degrading timing?

The outputs are characterized up to CL = 30 pF. At VCC = 3.3 V, tpd increases from 4.4 ns (CL = 5 pF) to 8.3 ns (CL = 30 pF); fmax drops from 550 MHz to 309 MHz. For timing-critical paths, keep CL ≤15 pF to maintain tpd ≤6.1 ns and fmax ≥480 MHz.

Is pin 1 marking visible on the 74AUP2G80DC-Q100 VSSOP8 package?

Yes. Per datasheet Table 2, the marking code "p80" appears adjacent to pin 1, which is indicated by a dot or notch in the lower-left corner of the package body-below the marking code-as confirmed in Figure 7's package outline and pin 1 index detail.