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Nexperia USA Inc. 74AUP2G80GS,115

Part No.:
74AUP2G80GS,115
Manufacturer:
Nexperia USA Inc.
Category:
Flip Flops
Package:
8-XFDFN
Datasheet:
Aetrix74AUP2G80GS,115.pdf
Description:
IC FF D-TYPE DUAL 1BIT 8XSON
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:88,800

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Product details

Overview

74AUP2G80GS,115 from Nexperia is a low-power dual positive-edge-triggered D-type flip-flop in an XSON8 package (1.35 × 1.0 × 0.35 mm, SOT1203), operating from 0.8 V to 3.6 V supply. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and guaranteed operation from –40 °C to +125 °C. Used in voltage-scalable logic interfacing, clock domain synchronization, and low-power sensor interface circuits.

For engineers reviewing the 74AUP2G80GS,115 datasheet, 74AUP2G80GS,115 pinout, 74AUP2G80GS,115 application, or 74AUP2G80GS,115 equivalent, key selection criteria include ultra-low ICC (≤1.4 μA max), sub-1 ns setup/hold times at 3.3 V, IOFF-enabled system-level power gating, and compatibility with 1.2 V, 1.8 V, and 3.3 V logic families.

Technical Context

This device implements two independent D-type flip-flops, each sampling data on the LOW-to-HIGH clock transition with input stability required one setup time prior. The Schmitt-trigger inputs ensure robust operation across slow-rising signals and full VCC range (0.8–3.6 V), eliminating external hysteresis components.

IOFF circuitry actively disables outputs when VCC = 0 V, blocking backflow current during partial power-down - critical for battery-backed subsystems and hot-swap interfaces. Propagation delay ranges from 1.2 ns (VCC = 3.3 V, CL = 5 pF) to 8.3 ns (VCC = 3.3 V, CL = 30 pF), supporting clock frequencies up to 510 MHz at 3.3 V.

Key Specifications

Parameter Value and Actual Design Meaning
Supply Voltage 0.8 V to 3.6 V - enables direct interfacing with 1.2 V, 1.8 V, and 3.3 V logic domains without level shifters
Max ICC (Static) 1.4 μA at –40 °C to +125 °C - supports always-on monitoring nodes in energy-constrained IoT endpoints
IOFF Leakage ±0.75 μA at VCC = 0 V - prevents destructive back-current during mixed-voltage power sequencing
tsu(H) / th 0.4 ns / 0 ns at VCC = 3.3 V - allows tight timing closure in high-speed control loops with minimal margin
fmax 510 MHz at VCC = 3.3 V, CL = 5 pF - suitable for clock-domain crossing in FPGA peripheral bridges and serial link deserializers
ESD Rating HBM > 5000 V, CDM > 1000 V - meets industrial handling requirements without additional board-level protection
Operating Temp –40 °C to +125 °C - qualified for under-hood automotive modules and industrial motor drives

Pinout & Package

XSON8 package (SOT1203): extremely thin small outline, no leads, 8-terminal surface-mount, body dimensions 1.35 mm × 1.0 mm × 0.35 mm, wettable flank compatible.

Pin/Terminal Circuit Role Design Meaning
1, 5 1CP, 2CP Independent clock inputs - enable asynchronous triggering of each flip-flop; edge-sensitive, Schmitt-triggered
2, 6 1D, 2D Data inputs - sampled on rising clock edge; tolerate slow edges and rail-to-rail input voltages up to 3.6 V
3, 7 2Q, 1Q Complementary Q outputs - non-inverting outputs with rail-to-rail swing and ±4 mA drive capability
4 GND Digital ground reference - must be connected directly to low-impedance PCB ground plane for noise immunity
8 VCC Power supply - decoupling capacitor (100 nF) required within 2 mm for stable high-frequency operation

Key Features

Feature Design Value
Wide VCC Range 0.8 V to 3.6 V - eliminates need for separate voltage regulators in multi-rail systems like wearables and smart sensors
Schmitt-Trigger Inputs Input hysteresis ≥0.3 V typical - rejects EMI-induced glitches on long PCB traces or flex cables without external RC filtering
IOFF Power-Down Mode Outputs disabled at VCC = 0 V - enables safe isolation of powered-down logic blocks in modular power architectures
Ultra-Low ICC ≤1.4 μA max over full temperature range - extends battery life in coin-cell-powered remote controls and environmental monitors
High-Speed Operation 510 MHz fmax at 3.3 V - supports real-time sampling of 250+ MHz digital signals in test equipment front-ends

Applications

Industrial Sensor Interface Automotive Body Control Module

Use Scenario: Level-shifting and synchronizing analog sensor ADC outputs (e.g., thermistor, pressure) into a 1.8 V microcontroller domain.

IC Role / Device Role: Dual D-flip-flop used as synchronized input register and metastability-hardened latch for asynchronous data capture.

Use Value: Eliminates need for discrete level shifters and reduces BOM count by integrating dual-channel synchronization with <1 ns timing uncertainty.

Use Scenario: Debouncing and edge-detection of mechanical switch inputs (door lock, seat position) in 12 V vehicle systems with 3.3 V MCU.

IC Role / Device Role: Positive-edge triggered storage element capturing switch state transitions while rejecting contact bounce noise.

Use Value: Schmitt-trigger inputs suppress >100 ns bounce without external RC networks; IOFF prevents leakage during sleep mode.

FPGA Configuration Bridge Low-Power Wearable Controller

Use Scenario: Glue logic between FPGA I/O banks (1.2 V/1.8 V) and legacy peripherals (3.3 V SPI EEPROM, UART transceivers).

IC Role / Device Role: Dual flip-flop providing synchronous domain crossing and output enable control for bidirectional data paths.

Use Value: Sub-2 ns propagation delay ensures timing closure across 100+ MHz control buses; 0.8 V minimum VCC supports future ultra-low-voltage FPGAs.

Use Scenario: Real-time activity counter in hearable devices using accelerometer interrupts routed to a 1.2 V ARM Cortex-M0+ core.

IC Role / Device Role: Edge-triggered latch capturing motion detection pulses while maintaining <2 μA total system standby current.

Use Value: 0.9 μA typical ICC at 1.2 V enables multi-week battery life; XSON8 footprint (1.35 × 1.0 mm) fits constrained PCB areas.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual D-type flip-flop applications.

Alternative Part Technical Difference Application Difference Selection Advice
SN74LVC2G74DCUR Higher ICC (10 μA typ), no IOFF, 1.65–5.5 V VCC range Lacks partial power-down support; unsuitable for mixed-voltage hot-swap systems Select when interfacing with 5 V peripherals and IOFF is not required
74LVC2G74GM,132 Same XSON8 package but rated only to +85 °C; no Schmitt inputs Lower noise immunity on slow-rising signals; not qualified for under-hood automotive use Select for cost-sensitive consumer applications with ambient temperature <85 °C

Compared with SN74LVC2G74DCUR and 74LVC2G74GM,132, the 74AUP2G80GS,115 uniquely combines ultra-low static power, IOFF, Schmitt inputs, and extended temperature range - making it the only choice for battery-powered automotive and industrial edge nodes requiring robust, scalable logic interfacing.

Availability

74AUP2G80GS,115 is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control, FPGA configuration bridge, and low-power wearable controller applications requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP2G80GS,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume applications.

The 74AUP (Advanced Ultra-low Power) logic family targets energy-constrained systems where dynamic and static power minimization, wide voltage scalability, and robust signal integrity are mandatory design requirements.

FAQ

Does 74AUP2G80GS,115 support true bidirectional data flow?

No. It is a unidirectional D-type flip-flop with dedicated D inputs and Q outputs. Each channel operates independently: data flows from D to Q on the rising clock edge. For bidirectional bus control, external direction logic or dedicated bus switches are required.

Can 74AUP2G80GS,115 be used with 0.8 V microcontrollers?

Yes. Its guaranteed operation down to 0.8 V VCC enables direct interface with ultra-low-voltage MCUs such as the Renesas RL78/G1M or STMicroelectronics STM32U0, eliminating level-shifting overhead while maintaining 1.4 μA max ICC at full temperature range.

What is the significance of the 'pT' marking on the 74AUP2G80GS,115 package?

The 'pT' marking per Table 2 identifies the device as either 74AUP2G80GN or 74AUP2G80GS. Pin 1 is located in the lower-left corner below the marking. This distinguishes it from 'p80'-marked variants (74AUP2G80DC/GT) and confirms SOT1203 package compliance.

How does IOFF behave when VCC is ramping during power-up?

IOFF activates only when VCC reaches ≤0.2 V. During power-up (VCC rising), outputs remain functional and follow standard logic behavior. IOFF does not engage during brown-out or partial ramp conditions - it is strictly active only in fully powered-down states (VCC ≈ 0 V).

74AUP2G80GS,115 Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
74AUP
Package/Case:
8-XFDFN
Packaging:
Bulk
Product Status:
Active
Function:
Standard
Type:
D-Type
Output Type:
Inverted
Number of Elements:
2
Number of Bits per Element:
1
Clock Frequency:
309 MHz
Max Propagation Delay @ V, Max CL:
6.4ns @ 3.3V, 30pF
Trigger Type:
Positive Edge
Current - Output High, Low:
4mA, 4mA
Voltage - Supply:
0.8V ~ 3.6V
Current - Quiescent (Iq):
500 nA
Input Capacitance:
0.6 pF
Operating Temperature:
-40°C ~ 125°C (TA)
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
8-XSON (1.35x1)

74AUP2G80GS,115 FAQ

1.How can I place an order for 74AUP2G80GS,115 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP2G80GS,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP2G80GS,115 reliable?

The price and inventory of 74AUP2G80GS,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G80GS,115 is usually 5 days.

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74AUP2G80GS,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP2G80GS,115 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP2G80GS,115?

For technical support, including 74AUP2G80GS,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G80GS,115 requirements.

6.How does Aetrix verify that 74AUP2G80GS,115 is sourced from the original manufacturer or authorized distributors?

All 74AUP2G80GS,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G80GS,115 meets industry standards.

7.What is the process for return or replacement of 74AUP2G80GS,115?

All 74AUP2G80GS,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G80GS,115, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP2G80GS,115 part is unused and in its original packaging.

Return procedure for 74AUP2G80GS,115:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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