Nexperia USA Inc. 74AUP2G86DC,125

Overview

74AUP2G86DC from Nexperia is a low-power dual 2-input EXCLUSIVE-OR gate in VSSOP8 package, operating across 0.8 V to 3.6 V supply, featuring Schmitt-trigger inputs for noise immunity and IOFF circuitry for partial power-down protection. It delivers propagation delay as low as 1.0 ns at 3.6 V (CL = 5 pF) and static ICC ≤ 1.4 μA over –40 °C to +125 °C, enabling use in battery-powered sensor interfaces and level-shifting logic in portable industrial controllers.

For engineers reviewing the 74AUP2G86DC datasheet, 74AUP2G86DC pinout, 74AUP2G86DC application, or 74AUP2G86DC equivalent, key selection criteria include its ultra-low ICC, wide VCC range compatibility with mixed-voltage systems, Schmitt-trigger input hysteresis for slow-edge signal conditioning, and IOFF-enabled backflow prevention during power sequencing.

Technical Context

This device implements two independent XOR gates with Schmitt-trigger inputs-each exhibiting hysteresis (ΔV ≈ 0.2–0.4 V depending on VCC) to reject noise on slow-rising/falling signals. Input thresholds scale with VCC (e.g., VIH = 0.70×VCC min at 0.8 V), ensuring robust operation across sub-1 V to 3.6 V rails.

The IOFF feature actively disables outputs when VCC = 0 V, limiting leakage to ±0.75 μA and preventing damaging backflow current into powered-down sections-a critical capability for hot-swap and multi-rail power management in embedded control modules.

Key Specifications

Pinout & Package

VSSOP8 package (SOT765-1): plastic very thin shrink small outline, 8 leads, 2.3 mm body width, 0.5 mm pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 2-input XOR gate applications.

Compared with 74LVC2G86DC, the 74AUP2G86DC offers superior noise immunity and 30× lower static power, while SN74AUP2G86DCKR provides identical performance with alternate supply-chain assurance-making it ideal for long-lifecycle industrial programs requiring vendor flexibility.

Availability

74AUP2G86DC is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power wearable logic, automotive body control modules, and programmable logic glue applications requiring stable component supply across extended temperature ranges and multi-year production cycles.

Supply support for 74AUP2G86DC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, with leadership in energy-efficient and automotive-qualified components.

The 74AUP (Advanced Ultra Low Power) logic family targets battery-operated and thermally constrained applications, emphasizing sub-μA static current, wide VCC scalability, and robust IOFF behavior for modern mixed-signal systems.

FAQ

Does 74AUP2G86DC support true 0.8 V logic operation with guaranteed timing?

Yes. The device is fully characterized from 0.8 V to 3.6 V, with propagation delay specified down to 21.2 ns at 0.8 V (CL = 5 pF) and input thresholds defined as fractions of VCC (e.g., VIH = 0.70×VCC min). All static and dynamic parameters-including IOFF activation and Schmitt hysteresis-are validated across this full range per JEDEC JESD8 standards.

Can 74AUP2G86DC inputs safely accept 5 V signals when VCC = 3.3 V?

No. Inputs are rated for voltages up to 3.6 V absolute maximum, and the datasheet explicitly states "Inputs accept voltages up to 3.6 V" - not 5 V. Applying 5 V risks exceeding the absolute maximum input voltage (VI = –0.5 V to +4.6 V), potentially causing latch-up or accelerated degradation. External level translation is required for 5 V interface.

How does IOFF behave during power sequencing when VCC ramps from 0 V to nominal?

IOFF activates automatically when VCC falls below ~0.2 V, disabling both outputs and limiting leakage to ±0.75 μA. During power-up, outputs remain in high-impedance until VCC exceeds ~0.5 V, then transition to active operation with full logic functionality. This behavior is intrinsic and requires no external control signals or biasing.

Is the VSSOP8 (SOT765-1) package of 74AUP2G86DC compatible with standard 0.5 mm pitch reflow profiles?

Yes. The SOT765-1 package has 0.5 mm lead pitch, 0.23 mm nominal lead width, and 0.27 mm max lead thickness, conforming to IPC-7351B density level 'N'. It is qualified for standard SnPb and lead-free reflow profiles (J-STD-020), including peak temperatures up to 260 °C for 10 seconds, with verified solder joint reliability per JEDEC JESD22-A113.