Nexperia USA Inc. 74AUP2G86GM,125

Overview

74AUP2G86GM,125 from Nexperia is a low-power dual 2-input XOR gate logic IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering 1.0 ns typical propagation delay at 3.3 V (CL = 5 pF), ICC ≤ 1.4 μA max over –40 °C to +125 °C, and IOFF-enabled partial power-down protection. It serves in voltage-level translation, noise-immune signal conditioning, and battery-powered interface logic in portable instrumentation and IoT sensor nodes.

For engineers reviewing the 74AUP2G86GM,125 datasheet, 74AUP2G86GM,125 pinout, 74AUP2G86GM,125 application, or 74AUP2G86GM,125 equivalent, key selection criteria include ultra-low static current (<1.4 μA), wide-VCC Schmitt-trigger input hysteresis, IOFF leakage control (<±0.75 μA), XQFN8 package thermal performance, and guaranteed operation up to +125 °C ambient.

Technical Context

This device implements two independent 2-input exclusive-OR gates in a single monolithic CMOS structure, each with Schmitt-trigger inputs enabling robust operation under slow-rising or noisy signals across its full 0.8–3.6 V VCC range. Input hysteresis ensures clean switching even with degraded edge rates.

The IOFF circuit actively disables outputs during power-down, limiting backflow current to ±0.75 μA when VCC = 0 V and any I/O is biased to 0–3.6 V - critical for hot-swap and multi-rail system interoperability. All inputs tolerate 3.6 V regardless of VCC level, supporting mixed-voltage domain interfacing.

Key Specifications

Pinout & Package

XQFN8 package (SOT902-1): 1.35 mm × 1.0 mm × 0.35 mm body, 0.4 mm pitch, wettable flank terminals, exposed thermal pad (pin 9) - optimized for space-constrained PCB layouts and thermal reliability in high-density designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 2-input XOR gate applications.

Compared with 74AUP2G86GM,125, the LVC variant trades ultra-low power for wider availability and lower cost but forfeits IOFF and sub-1 V operation; the TI USON-8 offers identical logic performance but constrains mechanical integration in <0.4 mm Z-height assemblies.

Availability

74AUP2G86GM,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power wearable logic, automotive body control modules, and IoT edge node signal conditioning requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP2G86GM,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and discrete components with industry-leading quality and reliability.

The 74AUP (Advanced Ultra-low Power) product line targets battery-sensitive and thermally constrained applications, emphasizing sub-μA static current, wide-VCC compatibility, and robust IOFF functionality for modern multi-rail systems.

FAQ

What is the maximum allowable input voltage on pins 1A/1B/2A/2B when VCC = 0 V?

The absolute maximum input voltage rating is –0.5 V to +4.6 V per Table 5, and inputs tolerate up to 3.6 V regardless of VCC level. With VCC = 0 V, the IOFF circuit blocks output current, but input clamping diodes remain active - applying >3.6 V risks exceeding IIK limit (–50 mA), so 3.6 V is the safe functional ceiling.

Does the 74AUP2G86GM,125 support true bidirectional signal routing?

No - it is a unidirectional logic gate with defined inputs (1A/1B/2A/2B) and outputs (1Y/2Y). While IOFF disables outputs during power-down, the device lacks internal pass-transistor architecture or direction-control pins required for bidirectional data flow like bus switches or transceivers.

Can this device drive a 50 pF capacitive load reliably at 3.3 V?

Yes - though not characterized in datasheet tables beyond 30 pF, the output drive strength (±4 mA) and low VOL/VOH ensure valid logic levels into 50 pF. Propagation delay increases to ~8.5 ns (extrapolated from CL = 30 pF data), remaining within most 25 MHz system timing budgets.

Is the exposed thermal pad (pin 9) electrically connected internally?

No - the exposed pad in SOT902-1 (XQFN8) is a non-electrical thermal slug tied solely to the die attach paddle. It must be soldered to a PCB thermal pad connected to GND or a dedicated thermal plane for optimal heat dissipation, but no electrical connection exists to internal circuitry.