Nexperia USA Inc. 74AUP2G86GN,115

Overview

74AUP2G86GN,115 from Nexperia is a low-power dual 2-input XOR gate in XSON8 package (1.2 × 1.0 × 0.35 mm), operating from 0.8 V to 3.6 V supply, featuring Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and guaranteed operation from –40 °C to +125 °C. It delivers sub-1.4 μA max ICC at full temperature range and supports logic-level translation across voltage domains in battery-powered sensor interfaces.

For engineers reviewing the 74AUP2G86GN,115 datasheet, 74AUP2G86GN,115 pinout, 74AUP2G86GN,115 application, or 74AUP2G86GN,115 equivalent, this device is selected for ultra-low-quiescent-power digital signal conditioning in space-constrained industrial IoT nodes, wearables, and portable instrumentation where input rise/fall time tolerance and supply voltage flexibility are critical.

Technical Context

This dual XOR gate implements two independent 2-input exclusive-OR functions with Schmitt-trigger inputs-ensuring robust switching even with slow or noisy signals across its full 0.8–3.6 V VCC range. Each gate exhibits symmetric propagation delay (tpd = tPLH = tPHL) and supports bidirectional level shifting due to input tolerance up to 3.6 V regardless of VCC.

The IOFF circuit actively disables outputs during power-down, limiting backflow current to ±0.75 μA at VCC = 0 V, enabling safe hot-insertion and multi-rail system partitioning. Input hysteresis (ΔV = ~0.2 V typical at VCC = 1.8 V) and low dynamic power (CPD = 3.1 pF at 1.8 V) make it suitable for high-noise mixed-signal environments.

Key Specifications

Pinout & Package

XSON8 package (SOT1116): extremely thin small outline, no leads, 8 terminals, body size 1.2 mm × 1.0 mm × 0.35 mm, pin 1 index located on lower-left corner below marking "pH".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 2-input XOR gate applications.

Compared with SN74LVC2G86DCUR and 74LVC2G86GM,132, the 74AUP2G86GN,115 uniquely combines ultra-low ICC, Schmitt inputs, full –40 °C to +125 °C rating, and 0.8 V operation - making it the sole choice for energy-constrained, high-temperature, or electrically noisy embedded designs.

Availability

74AUP2G86GN,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable biometric monitoring, automotive body control modules, and portable test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP2G86GN,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume electronics.

The 74AUP (Advanced Ultra-low Power) family targets battery-operated and thermally constrained applications, emphasizing sub-μA static current, wide VCC scalability, and robust IOFF behavior for modern multi-rail systems.

FAQ

Does 74AUP2G86GN,115 support true bidirectional level translation?

No - it supports unidirectional level translation only: inputs accept 0–3.6 V regardless of VCC, but outputs swing between GND and VCC. For true bidirectional translation (e.g., I²C), a dedicated bus switch or analog switch is required. The device does not pass signals from output to input.

Can pin 1 (1A) be left floating in unused gate configuration?

No - all inputs must be terminated to a defined logic level (VCC or GND) to prevent increased ICC, oscillation, or ESD susceptibility. Floating inputs cause undefined internal node voltages and may exceed II leakage limits. Tie unused 1A/1B to GND or VCC via ≤10 kΩ resistor.

What is the maximum capacitive load the outputs can drive reliably?

The outputs are characterized up to 30 pF load capacitance (see Table 8). Driving >30 pF increases tpd nonlinearly and may cause overshoot/undershoot exceeding 10 % of VCC. For >50 pF loads, add series termination or buffer stage to maintain signal integrity and timing margins.

Is the IOFF function active during brown-out conditions (VCC < 0.8 V but > 0 V)?

Yes - IOFF activates when VCC drops below the functional threshold (~0.5 V), clamping output leakage to ±0.75 μA even during gradual brown-out. This prevents back-current from downstream 3.3 V rails into the partially powered device, protecting both ICs and PCB traces.