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Nexperia USA Inc. 74AUP2G97DPJ
- Part No.:
- 74AUP2G97DPJ
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
74AUP2G97DPJ.pdf
- Description:
- IC GATE DUAL PCB MULTI 10TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,372
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Product details
Overview
74AUP2G97DP from Nexperia is a dual configurable multiple-function logic gate with Schmitt-trigger inputs, supporting MUX, AND, OR, NAND, NOR, inverter, and buffer configurations per gate via 3-bit function select. It operates from 0.8 V to 3.6 V, delivers ≤0.9 μA max ICC at 125 °C, and features IOFF for partial power-down protection. Used in low-power PCB-level signal routing and level-shifting in battery-powered sensor nodes.
For engineers reviewing the 74AUP2G97DP datasheet, 74AUP2G97DP pinout, 74AUP2G97DP application, or 74AUP2G97DP equivalent, this page provides verified functional configuration modes, TSSOP10 pin mapping, Schmitt-trigger noise immunity specs, and real-world use cases in mixed-voltage digital interfacing.
Technical Context
The device implements two independent configurable gates, each accepting three control inputs (nA/nB/nC) to select one of seven logic functions. Each gate has Schmitt-trigger inputs with hysteresis (VH = 0.07–1.31 V depending on VCC), enabling robust noise rejection in noisy environments.
IOFF circuitry disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA, making it suitable for hot-swap and partial-power-down systems. Input voltage tolerance extends to 3.6 V regardless of VCC, supporting mixed-supply domain interfacing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 0.8 V to 3.6 V - enables operation across ultra-low-voltage microcontrollers (e.g., 1.2 V ARM Cortex-M0+) and 3.3 V I/O domains. |
| Max ICC (125 °C) | 0.9 μA - ensures sub-1 μA static power in always-on monitoring circuits without compromising logic integrity. |
| Propagation Delay | 1.5 ns (min) to 4.3 ns (max) at VCC = 3.0–3.6 V, CL = 5 pF - supports >200 MHz toggle rates in compact timing-critical paths. |
| Input Hysteresis (VH) | 0.79–1.31 V at VCC = 3.0 V - rejects >1.3 V peak-to-peak noise on slow-rising signals (e.g., mechanical switch debouncing). |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents >100 nA backfeed into powered-down subsystems, satisfying IEC 62368-1 isolation requirements. |
| ESD Rating | HBM >5000 V, CDM >1000 V - withstands handling and board-level ESD events without latch-up or parameter shift. |
| Operating Temp | −40 °C to +125 °C - qualified for under-hood automotive modules and industrial edge controllers without derating. |
Pinout & Package
TSSOP10 package (SOT552-1), 3 mm body width, 0.5 mm pitch, exposed pad not present. Pin 1 index located below marking code in lower-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A, 2A | Data input A (Gate 1 / Gate 2) | Primary data path input; accepts 0–3.6 V regardless of VCC; Schmitt-triggered for noise margin. |
| 1B, 2B | Data input B (Gate 1 / Gate 2) | Secondary data input; used with 1A/2A and 1C/2C to define logic function per gate (e.g., MUX select). |
| 1C, 2C | Function select input C (Gate 1 / Gate 2) | Third control bit determining logic mode; tied high/low to fix function without external control lines. |
| 1Y, 2Y | Output Y (Gate 1 / Gate 2) | Configurable logic output; drives 4 mA at VCC = 3.0 V; IOFF active when VCC = 0 V. |
| VCC | Power supply | Single supply rail; powers both gates and internal configuration logic; supports dynamic voltage scaling. |
| GND | Ground reference | 0 V return for all inputs, outputs, and internal circuitry; must be low-impedance for stable Schmitt thresholds. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent configurable gates | Each gate independently programmed via 3-pin select (nA/nB/nC); eliminates need for multiple discrete logic ICs on space-constrained PCBs. |
| Schmitt-trigger inputs with programmable hysteresis | VH = 0.79–1.31 V at 3.0 V VCC - suppresses chatter on slow edges from sensors or long traces without external RC filtering. |
| IOFF-enabled partial power-down | Outputs float safely when VCC = 0 V; prevents back-current into powered subsystems during sleep or fault isolation. |
| Wide-input voltage tolerance | Inputs accept up to 3.6 V even at VCC = 0.8 V - enables direct connection to 3.3 V GPIOs driving 0.8 V logic domains without level shifters. |
| Low-noise switching | Overshoot/undershoot <10 % of VCC - reduces EMI in EMC-sensitive applications like medical wearables and IoT gateways. |
Applications
| Industrial Sensor Interface | Portable Medical Device Logic |
|---|---|
|
Use Scenario: Interfacing analog sensor outputs (e.g., thermistor divider) to a low-power MCU ADC with variable sampling rate. IC Role / Device Role / Timing Role: Configured as inverter + buffer pair to condition and isolate slow-rising sensor signals while rejecting line noise. Use Value: Eliminates external RC filters and discrete buffers; Schmitt thresholds ensure clean transitions at <1 kHz update rates. |
Use Scenario: Managing button debounce and LED driver enable sequencing in a battery-powered pulse oximeter. IC Role / Device Role / Timing Role: One gate as 2-input NAND (for button+timer logic), second as buffer (to drive LED anode with 4 mA sink capability). Use Value: Reduces BOM count by 2 components; 0.9 μA ICC extends battery life beyond 12 months in standby mode. |
| Automotive Body Control Module | Smart Home Hub Signal Routing |
|
Use Scenario: Level-shifting and signal conditioning between 5 V legacy CAN transceiver status pins and 3.3 V microcontroller GPIOs. IC Role / Device Role / Timing Role: Configured as buffer with 3.6 V-tolerant inputs to accept 5 V open-drain signals; IOFF protects MCU during ignition-off state. Use Value: Avoids dedicated level translators; IOFF leakage <0.75 μA meets ISO 11898-2 quiescent current limits for always-connected modules. |
Use Scenario: Dynamic reconfiguration of Zigbee/Thread radio interface signals based on active wireless protocol. IC Role / Device Role / Timing Role: Gate 1 as 2-input MUX selecting between antenna switch control lines; Gate 2 as OR gate combining interrupt sources. Use Value: Enables single-hardware design for multi-protocol hubs; propagation delay <4.3 ns ensures timing compliance at 2.4 GHz PHY layer handshaking. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar configurable logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G97DCUR | Wider VCC range (1.65–5.5 V); higher ICC (max 10 μA); no IOFF; standard CMOS (no Schmitt inputs) | Requires external hysteresis for noisy inputs; unsuitable for partial power-down systems | Select when interfacing 5 V peripherals and Schmitt functionality is unnecessary |
| 74AUP2G17GW,125 | Dual Schmitt-trigger buffer only; fixed function; no configurability; same VCC range and ICC | Lacks MUX/AND/OR flexibility; simpler layout but requires additional logic for function changes | Select when only noise-immune buffering is needed and PCB space allows separate function ICs |
Compared with SN74LVC2G97DCUR and 74AUP2G17GW,125, the 74AUP2G97DP uniquely combines Schmitt-trigger noise immunity, ultra-low ICC, IOFF protection, and on-the-fly logic reconfiguration - critical for miniaturized, battery-operated, and mixed-voltage embedded systems where component count and power budget are constrained.
Availability
74AUP2G97DP is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, automotive body control modules, and smart home hub signal routing requiring stable component supply across extended temperature ranges.
Supply support for 74AUP2G97DP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in consumer, industrial, and automotive markets.
The 74AUP (Advanced Ultra-low Power) product line targets energy-constrained applications demanding sub-μA static current, wide VCC scalability, and robust signal integrity - especially in battery-powered and thermally restricted environments.
FAQ
Can the 74AUP2G97DP be used with VCC = 0.8 V and 3.3 V inputs simultaneously?
Yes. Inputs tolerate up to 3.6 V regardless of VCC level, so 3.3 V GPIOs can directly drive 1A/1B/1C pins while VCC = 0.8 V. This enables seamless interfacing between legacy 3.3 V subsystems and emerging ultra-low-voltage processors without level shifters or voltage dividers.
How does the IOFF feature behave during power sequencing?
When VCC drops to 0 V, IOFF activates within nanoseconds, disabling both outputs (1Y/2Y) and limiting leakage to ±0.75 μA. This prevents back-current flow into powered-down sections - critical for systems with asymmetric power rails or hot-plug modules where VCC may be sequenced independently.
What is the minimum load capacitance supported for guaranteed timing performance?
The propagation delay specs (e.g., 1.5–4.3 ns) are validated down to CL = 5 pF. For loads <5 pF, delays improve marginally but are not characterized; designs should maintain ≥5 pF (including PCB trace capacitance) to ensure timing compliance per datasheet limits across −40 °C to +125 °C.
Is the function selection latched or combinatorial?
Function selection is fully combinatorial: the logic output (nY) responds immediately to changes in nA/nB/nC inputs with no internal storage. There is no latch or register - behavior matches standard combinational logic, enabling real-time reconfiguration during operation without clocking or setup/hold constraints.
74AUP2G97DPJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Configurable Multiple Function
- Number of Circuits:
- 2
- Number of Inputs:
- 3
- Schmitt Trigger Input:
- Yes
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-TSSOP
74AUP2G97DPJ FAQ
1.How can I place an order for 74AUP2G97DPJ through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G97DPJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G97DPJ reliable?
The price and inventory of 74AUP2G97DPJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G97DPJ is usually 5 days.
3.What payment methods are accepted for 74AUP2G97DPJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G97DPJ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP2G97DPJ?
74AUP2G97DPJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G97DPJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G97DPJ?
For technical support, including 74AUP2G97DPJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G97DPJ requirements.
6.How does Aetrix verify that 74AUP2G97DPJ is sourced from the original manufacturer or authorized distributors?
All 74AUP2G97DPJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G97DPJ meets industry standards.
7.What is the process for return or replacement of 74AUP2G97DPJ?
All 74AUP2G97DPJ units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G97DPJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G97DPJ part is unused and in its original packaging.
Return procedure for 74AUP2G97DPJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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