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NXP Semiconductors 74AUP2G97GF115
- Part No.:
- 74AUP2G97GF115
- Manufacturer:
- NXP Semiconductors
- Package:
- 10-XFDFN
- Datasheet:
-
74AUP2G97GF115.pdf
- Description:
- MAJORITY LOGIC GATE
- Quantity:
- Payment:
- Shipping:
Inventory:3,723
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Product details
Overview
74AUP2G97GF115 from NXP Semiconductors is a dual configurable multiple-function logic gate with Schmitt-trigger inputs, supporting MUX, AND, OR, NAND, NOR, inverter, and buffer configurations via 3-bit select inputs. It operates from 0.8 V to 3.6 V, delivers ≤1.4 µA max ICC across −40 °C to +125 °C, and features IOFF for partial power-down protection. It is used in low-power PCB-level logic reconfiguration for sensor interface and control signal conditioning.
For engineers reviewing the 74AUP2G97GF115 datasheet, 74AUP2G97GF115 pinout, 74AUP2G97GF115 application, or 74AUP2G97GF115 equivalent, key selection criteria include its ultra-low static current, Schmitt-trigger noise immunity, IOFF-enabled power-gating capability, and XSON10 (SOT1081-2) 10-terminal package with 1.0 × 1.7 × 0.5 mm footprint.
Technical Context
The 74AUP2G97GF115 implements two independent configurable gates, each selectable among seven logic functions using three dedicated configuration inputs (nA/nB/nC). Its Schmitt-trigger inputs provide hysteresis (e.g., 0.79 V at VCC = 3.0 V), enabling robust noise rejection in noisy digital environments.
IOFF circuitry actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 µA maximum and supporting hot-swap and partial power-down system architectures. The device is characterized across −40 °C to +125 °C with propagation delays as low as 1.5 ns (VCC = 3.0–3.6 V, CL = 5 pF).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage range | 0.8 V to 3.6 V - supports single-supply operation across battery-powered and mixed-voltage logic domains. |
| Max supply current (ICC) | 1.4 µA at −40 °C to +125 °C - enables multi-year operation in energy-harvesting and always-on monitoring systems. |
| IOFF leakage current | ±0.75 µA at VCC = 0 V - prevents damaging back-current during power sequencing or partial shutdown. |
| Propagation delay (tpd) | 1.5 ns min (VCC = 3.0–3.6 V, CL = 5 pF) - meets timing-critical signal routing in compact embedded controllers. |
| Input hysteresis (VH) | 0.79 V typical at VCC = 3.0 V - rejects >700 mV of input noise without external filtering components. |
| ESD protection | HBM >5000 V, CDM >1000 V - withstands handling and board-level ESD events without shielding. |
| Operating temperature | −40 °C to +125 °C - qualified for under-hood automotive, industrial motor control, and outdoor IoT nodes. |
Pinout & Package
74AUP2G97GF115 uses the XSON10 (SOT1081-2) package: plastic extremely thin small outline, no leads, 10 terminals, body size 1.0 × 1.7 × 0.5 mm. Pin 1 indicator is located on the lower-left corner below the marking code 'aV'.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 6 | 1A, 2A - data input | Primary logic inputs for Gate 1 and Gate 2; accept voltages up to 3.6 V regardless of VCC level. |
| 2, 7 | 1B, 2B - data input | Secondary logic inputs; Schmitt-triggered for noise-immune signal acquisition. |
| 3, 8 | 1C, 2C - configuration input | 3-bit select lines determining logic function per gate (MUX/AND/OR/NAND/NOR/inverter/buffer). |
| 4, 9 | 1Y, 2Y - data output | Configurable logic outputs with IOFF-enabled high-impedance state during power-down. |
| 5 | GND - ground | 0 V reference; decoupling capacitor placement adjacent to this pin minimizes switching noise. |
| 10 | VCC - supply voltage | Single power rail (0.8–3.6 V); powers both logic core and IOFF circuitry. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent configurable gates | Each gate programmable via 3-bit input to one of seven logic functions - eliminates need for multiple discrete logic ICs on PCB. |
| Schmitt-trigger inputs with hysteresis | VT+ − VT− ≥ 0.79 V at 3.0 V supply - enables reliable operation with slow-rising or noisy signals (e.g., mechanical switch debouncing). |
| IOFF partial power-down support | Outputs enter high-Z state when VCC = 0 V, blocking back-current - essential for I²C bus isolation and multi-rail power sequencing. |
| Ultra-low static power consumption | ICC ≤ 1.4 µA over full temperature range - extends battery life in portable medical sensors and wireless transceivers. |
| Wide operating temperature range | −40 °C to +125 °C - validated for engine control units, industrial PLC I/O modules, and solar inverter monitoring circuits. |
Applications
| Industrial Sensor Interface | Automotive Body Control Module |
|---|---|
Use Scenario: Signal conditioning for analog sensor outputs digitized by low-speed ADCs in factory-floor vibration monitors. IC Role / Device Role / Timing Role: Configured as inverter/buffer to drive ADC input with noise-immune logic levels; Schmitt-trigger inputs reject EMI from nearby motors. Use Value: Eliminates external RC filters and reduces BOM count while maintaining signal integrity across 0–10 kHz bandwidth. |
Use Scenario: Logic-level translation and debounce for door lock/unlock switch inputs in BCM subsystems. IC Role / Device Role / Timing Role: Configured as NAND gate with Schmitt-trigger inputs to reject contact bounce and supply-voltage ripple. Use Value: Reduces firmware debounce overhead and improves functional safety compliance by hardening input stage against transient faults. |
| Portable Medical Wearable | Smart Energy Metering |
Use Scenario: Power-state coordination between BLE SoC and optical heart-rate sensor in wrist-worn devices. IC Role / Device Role / Timing Role: Configured as 2-input MUX to route either sensor data or calibration signals to MCU; IOFF isolates sensor during sleep mode. Use Value: Enables sub-µA system standby current by cutting off sensor bias paths without modifying PCB layout. |
Use Scenario: Isolating tamper-detection circuitry from main metering SoC during brown-out conditions. IC Role / Device Role / Timing Role: Configured as OR gate with IOFF enabled to disconnect tamper signal path when VCC drops below 1.2 V. Use Value: Prevents false tamper alarms during grid voltage sags while preserving nonvolatile event logging capability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar configurable logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC2G97GM | Wider VCC range (1.65–5.5 V); higher ICC (max 10 µA); no IOFF; −40 °C to +125 °C. | Lacks power-down isolation; unsuitable for hot-swap or multi-rail sequencing. | Select when interfacing with 5 V logic and IOFF is not required. |
| SN74AUP2G97DCUR | TSSOP10 package (3 mm width); identical electrical specs; same marking 'aV'; −40 °C to +85 °C only. | Lower temperature rating limits use in under-hood or high-ambient industrial settings. | Select when board space allows TSSOP and extended temperature is unnecessary. |
Compared with 74LVC2G97GM and SN74AUP2G97DCUR, the 74AUP2G97GF115 uniquely combines ultra-low ICC (<1.4 µA), IOFF, and −40 °C to +125 °C qualification in a 1.0 × 1.7 mm XSON10 package - making it optimal for space-constrained, battery-sensitive, and thermally demanding applications.
Availability
74AUP2G97GF115 is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control, portable medical wearables, and smart energy metering requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP2G97GF115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The 74AUP2G97GF115 belongs to NXP's Advanced Ultra-low-power (AUP) logic family, designed specifically for energy-efficient PCB-level logic reconfiguration in battery-operated and thermally constrained systems.
FAQ
What logic functions does the 74AUP2G97GF115 support?
The 74AUP2G97GF115 supports seven configurable logic functions per gate: 2-input MUX, AND, OR, NAND, NOR, inverter, and buffer. Configuration is performed via three dedicated inputs (nA/nB/nC) per gate, with truth tables defined in the official NXP datasheet. Each of the two gates operates independently, enabling heterogeneous logic implementation on a single die.
Does the 74AUP2G97GF115 support partial power-down operation?
Yes, the 74AUP2G97GF115 includes integrated IOFF circuitry that disables outputs when VCC = 0 V, limiting backflow current to ±0.75 µA maximum. This feature enables safe partial power-down in multi-rail systems and hot-swap applications - a capability confirmed in Section 1 of the NXP datasheet and verified across −40 °C to +125 °C.
What is the package type and footprint of the 74AUP2G97GF115?
The 74AUP2G97GF115 uses the XSON10 (SOT1081-2) package: a leadless, extremely thin small outline package with 10 terminals and dimensions of 1.0 × 1.7 × 0.5 mm. Pin 1 is marked in the lower-left corner below the 'aV' marking code. This package is optimized for high-density PCB layouts in space-constrained applications.
What is the maximum supply current (ICC) specification for the 74AUP2G97GF115?
The maximum supply current (ICC) for the 74AUP2G97GF115 is 1.4 µA at −40 °C to +125 °C, as specified in Table 8 of the NXP datasheet. This value applies under recommended operating conditions (VI = GND or VCC, IO = 0 A, VCC = 0.8 V to 3.6 V) and reflects worst-case static consumption across the full industrial temperature range.
How does the Schmitt-trigger input improve noise immunity in the 74AUP2G97GF115?
The Schmitt-trigger inputs of the 74AUP2G97GF115 provide hysteresis (e.g., 0.79 V at VCC = 3.0 V), meaning the positive-going threshold (VT+) and negative-going threshold (VT−) differ significantly. This prevents oscillation on slow or noisy edges - such as those from mechanical switches or unfiltered sensor outputs - and eliminates the need for external RC filtering in many designs.
74AUP2G97GF115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 10-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Configurable Multiple Function
- Number of Circuits:
- 2
- Number of Inputs:
- 3
- Schmitt Trigger Input:
- Yes
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-XSON (1.7x1)
74AUP2G97GF115 FAQ
1.How can I place an order for 74AUP2G97GF115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G97GF115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G97GF115 reliable?
The price and inventory of 74AUP2G97GF115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G97GF115 is usually 5 days.
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Once your 74AUP2G97GF115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G97GF115?
For technical support, including 74AUP2G97GF115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G97GF115 requirements.
6.How does Aetrix verify that 74AUP2G97GF115 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G97GF115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G97GF115 meets industry standards.
7.What is the process for return or replacement of 74AUP2G97GF115?
All 74AUP2G97GF115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G97GF115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G97GF115 part is unused and in its original packaging.
Return procedure for 74AUP2G97GF115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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