Nexperia USA Inc. 74AUP2G98DPJ

Overview

74AUP2G98DP from Nexperia is a dual configurable multiple-function logic gate with Schmitt-trigger inputs, enabling each gate to be programmed as MUX, AND, OR, NAND, NOR, inverter, or buffer via 3-bit configuration inputs. It operates across 0.8 V–3.6 V supply, delivers ≤0.9 μA max ICC at 125 °C, supports partial power-down via IOFF, and targets low-power PCB-level logic reconfiguration in space-constrained industrial control and sensor interface modules.

For engineers reviewing the 74AUP2G98DP datasheet, 74AUP2G98DP pinout, 74AUP2G98DP application, or 74AUP2G98DP equivalent, this page provides verified functional identity, TSSOP10 pin mapping, Schmitt-trigger noise immunity specs, IOFF-enabled power-gating behavior, and validated alternatives for logic flexibility in battery-powered and thermally demanding embedded systems.

Technical Context

The device implements two independent configurable gates, each accepting three control inputs (nA/nB/nC) to select one of nine logic functions per gate, with all inputs tolerant up to 3.6 V regardless of VCC. Each gate features Schmitt-trigger inputs with hysteresis (VH = 0.07–1.31 V) and rail-to-rail output swing.

IOFF circuitry actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA over –40 °C to +125 °C, while propagation delay ranges from 1.6 ns (VCC = 3.3 V, CL = 5 pF) to 22.4 ns (VCC = 1.2 V, CL = 15 pF), ensuring timing predictability across voltage and temperature extremes.

Key Specifications

Pinout & Package

TSSOP10 package (SOT552-1): plastic thin shrink small outline, 10-lead, 3 mm body width, 0.5 mm pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with 74AUP2G98DP, the 74LVC2G98DP trades ultra-low power and IOFF for higher speed margin at 3.3 V, while SN74LVC1G98DCKR sacrifices integration density to match pin compatibility with legacy single-gate footprints - making 74AUP2G98DP uniquely suited for thermally aggressive, power-gated, dual-function applications.

Availability

74AUP2G98DP is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power wearables, automotive body control modules, and programmable test equipment requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP2G98DP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, power, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP2G98DP belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, engineered specifically for energy-sensitive, thermally demanding applications where dynamic reconfigurability and robust noise immunity are mandatory.

FAQ

What logic functions can each gate implement?

Each gate supports nine configurations: 2-input MUX with inverted output, 2-input NAND, 2-input NOR with one input inverted, 2-input AND with one input inverted, 2-input NAND with one input inverted, 2-input OR with one input inverted, 2-input NOR, buffer, and inverter - selected via the three dedicated control inputs (nA/nB/nC) per gate.

Does the 74AUP2G98DP support true 0 V operation during power-down?

Yes - its IOFF circuitry actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA across –40 °C to +125 °C. This prevents damage during hot-swap events or multi-rail sequencing where other supplies remain active while VCC is off.

Can inputs be tied directly to VCC or GND without pull-up/down resistors?

Yes - all inputs accept direct connection to VCC or GND. The device has no internal pull resistors, but the input structure tolerates full rail voltages and exhibits negligible leakage (±0.75 μA max), enabling hard-wired configuration for fixed-function use cases.

How does Schmitt-trigger hysteresis vary with supply voltage?

Hysteresis (VH = VT+ − VT−) scales with VCC: from 0.07 V at 0.8 V supply to 1.31 V at 3.0 V supply. This ensures consistent noise margin percentage-wise across the entire 0.8–3.6 V operating range, unlike standard CMOS inputs whose noise immunity degrades at lower VCC.