NXP Semiconductors 74AUP2G98GUX
- Part No.:
- 74AUP2G98GUX
- Manufacturer:
- NXP Semiconductors
- Package:
- 10-XFQFN
- Datasheet:
-
74AUP2G98GUX.pdf
- Description:
- NEXPERIA 74AUP2G98GU - MAJORITY
- Quantity:
- Payment:

- Shipping:

Inventory:77,465
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Product details
Overview
74AUP2G98GUX from Nexperia is a dual configurable multiple-function logic gate with Schmitt-trigger inputs, enabling per-gate selection of MUX, AND, OR, NAND, NOR, inverter, or buffer functions via 3-bit configuration inputs. It operates across 0.8 V to 3.6 V, delivers ≤0.9 μA max ICC at 25 °C, supports partial power-down via IOFF, and is rated for −40 °C to +125 °C. Used in low-power sensor interface and PCB-level signal conditioning circuits where voltage scalability and noise immunity are critical.
For engineers reviewing the 74AUP2G98GUX datasheet, 74AUP2G98GUX pinout, 74AUP2G98GUX application, or 74AUP2G98GUX equivalent, key selection criteria include its dual-gate configurability, sub-1 μA static current, IOFF-enabled power sequencing, and compatibility with 1.2 V/1.8 V/2.5 V/3.3 V logic domains in space-constrained industrial and portable electronics.
Technical Context
This device implements two independent, user-configurable logic gates, each accepting three control inputs (nA/nB/nC) to select one of eight Boolean functions. Each gate features Schmitt-trigger inputs with hysteresis (VH = 0.07–1.31 V depending on VCC), ensuring robust noise rejection in noisy environments.
Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V while inputs/outputs remain biased between 0 V and 3.6 V - a requirement for hot-swap and multi-rail system designs. The logic function table defines deterministic output behavior for all 8 input combinations, with propagation delays as low as 1.6 ns (VCC = 3.0 V, CL = 5 pF).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - enables direct interfacing with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic families without level shifters. |
| Max ICC (25 °C) | 0.9 μA - ensures ultra-low static power in battery-backed or energy-harvesting systems. |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - guarantees safe isolation during partial power-down without external pull resistors. |
| Propagation Delay (VCC = 3.0 V, CL = 5 pF) | 1.6–4.4 ns - supports timing-critical signal routing in high-speed digital subsystems. |
| Input Hysteresis (VH) | 0.07–1.31 V - provides ≥100 mV noise margin at 1.8 V supply, rejecting EMI-induced glitches. |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive modules and industrial motor controls. |
| ESD Rating (HBM) | 5000 V - eliminates need for external ESD protection in handheld and field-deployable equipment. |
Pinout & Package
XQFN10 (SOT1160-1) package: plastic, extremely thin quad flat no-lead package; 10 terminals; body size 1.40 × 1.80 × 0.50 mm; wettable flank terminals for automated optical inspection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A, 2A | Data Input A (per gate) | Primary data input for Gate 1 and Gate 2; accepts voltages up to 3.6 V regardless of VCC. |
| 1B, 2B | Data Input B (per gate) | Secondary data input; Schmitt-triggered for noise immunity in slow or noisy signal paths. |
| 1C, 2C | Configuration Input C (per gate) | Third bit of 3-bit function selector; determines logic mode together with 1A/1B or 2A/2B. |
| 1Y, 2Y | Output Y (per gate) | Configurable logic output; driven rail-to-rail with ±4 mA drive strength at 3.0 V. |
| VCC | Power Supply | Single supply pin supporting 0.8–3.6 V; powers both gates and internal configuration logic. |
| GND | Ground Reference | Common return path for all I/O and internal circuitry; must be low-impedance for stable operation. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent configurable gates | Each gate independently programmed via 3-bit input - enables mixed-function logic on single die, reducing PCB footprint vs discrete gates. |
| IOFF partial power-down | Outputs disabled with leakage < ±0.75 μA when VCC = 0 V - allows safe insertion/removal in live backplanes and multi-voltage systems. |
| Schmitt-trigger inputs | Hysteresis (VH) scalable with VCC (0.07–1.31 V) - rejects >100 mV noise spikes without external RC filtering. |
| Ultra-low static current | ICC ≤ 0.9 μA max at 25 °C - extends battery life in always-on IoT nodes and sensor transceivers. |
| Wide temperature range | Specified from −40 °C to +125 °C - supports deployment in automotive engine control units and industrial PLC I/O modules. |
Applications
| Industrial Sensor Interface | Portable Device Power Sequencing |
|---|---|
|
Use Scenario: Signal conditioning for analog sensor outputs in factory-floor vibration monitors with 1.8 V microcontrollers. IC Role / Device Role / Timing Role: Configured as Schmitt-trigger buffer to clean noisy ADC reference signals before digitization. Use Value: Eliminates external RC filters and saves 2.5 mm² PCB area versus discrete gate + hysteresis solution. |
Use Scenario: Enabling/disabling auxiliary rails in medical handheld ultrasound devices during sleep/wake transitions. IC Role / Device Role / Timing Role: Used as dual NAND gate to generate synchronized enable signals for LDOs with IOFF isolation. Use Value: Prevents backfeed current into powered-down subsystems, avoiding latch-up and system reset events. |
| Automotive Body Control Module | Low-Power Wireless Node |
|
Use Scenario: Debouncing mechanical switch inputs (door lock, trunk release) in 12 V vehicle architectures with 3.3 V domain logic. IC Role / Device Role / Timing Role: Configured as inverter with Schmitt input to reject contact bounce and EMI in unshielded harnesses. Use Value: Achieves >10 kV ESD robustness and 125 °C operation without derating - meets ISO 16750-2 pulse test requirements. |
Use Scenario: Logic-level translation and signal routing in BLE 5.0 beacon nodes powered by coin-cell batteries. IC Role / Device Role / Timing Role: Set as 2-input MUX to dynamically route wake-up sources (motion sensor or RF interrupt) to MCU GPIO. Use Value: Draws only 0.9 μA static current - extends 10-year battery life target while maintaining sub-5 ns switching latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar configurable logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G98DCUR | Wider VCC range (1.65–5.5 V); higher ICC (max 10 μA); no IOFF; −40 °C to +85 °C only. | Lacks partial power-down support; unsuitable for hot-swap or multi-rail sequencing. | Choose only if 5 V logic compatibility is required and power-down isolation is unnecessary. |
| 74AUP2G17GUX | Dual Schmitt-trigger buffer only; fixed function; ICC = 0.9 μA; same package/temp range. | No configurability - cannot implement MUX, NAND, or other logic modes. | Select when only noise-immune buffering is needed and design flexibility is not required. |
Compared with SN74LVC2G98DCUR and 74AUP2G17GUX, the 74AUP2G98GUX uniquely combines ultra-low ICC, IOFF, full configurability, and extended temperature range - making it the sole option for compact, low-power, multi-rail systems requiring dynamic logic reconfiguration.
Availability
74AUP2G98GUX is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable device power sequencing, automotive body control modules, and low-power wireless nodes requiring stable component supply across extended temperature and voltage ranges.
Supply support for 74AUP2G98GUX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and energy-sensitive applications, emphasizing sub-1 μA static current, wide VCC scalability, and robust IOFF functionality for modern multi-voltage system architectures.
FAQ
What logic functions can each gate implement?
Each gate supports eight configurations: 2-input MUX with inverted output, 2-input NAND, 2-input NOR with one input inverted, 2-input AND with one input inverted, 2-input NAND with one input inverted, 2-input OR with one input inverted, 2-input NOR, buffer, and inverter - selected deterministically by the 3-bit input combination (nC,nB,nA) per gate.
Does 74AUP2G98GUX support level shifting between different VCC domains?
No - it is a single-supply device with one VCC pin. Inputs tolerate up to 3.6 V regardless of VCC, but outputs swing only between GND and the applied VCC. For true bidirectional level shifting, external translators or dedicated level-shifters are required.
How does the IOFF feature behave during power-down?
When VCC = 0 V, the IOFF circuit disables both outputs (1Y and 2Y), limiting leakage to ±0.75 μA maximum even if inputs or outputs are biased to 3.6 V - preventing damaging backflow current and enabling safe operation in partial power-down states.
Is the XQFN10 (SOT1160-1) package compatible with standard reflow profiles?
Yes - the SOT1160-1 package is qualified for IPC/JEDEC J-STD-020 moisture sensitivity level 1 and supports standard lead-free reflow profiles (peak temperature ≤260 °C). Its wettable flanks enable reliable automated optical inspection of solder joints.
74AUP2G98GUX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 10-XFQFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Configurable Multiple Function
- Number of Circuits:
- 2
- Number of Inputs:
- 6 Input (3, 3)
- Schmitt Trigger Input:
- Yes
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-XQFN (1.4x1.8)
74AUP2G98GUX FAQ
1.How can I place an order for 74AUP2G98GUX through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G98GUX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G98GUX reliable?
The price and inventory of 74AUP2G98GUX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G98GUX is usually 5 days.
3.What payment methods are accepted for 74AUP2G98GUX?
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4.How is shipping managed for 74AUP2G98GUX?
74AUP2G98GUX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G98GUX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G98GUX?
For technical support, including 74AUP2G98GUX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G98GUX requirements.
6.How does Aetrix verify that 74AUP2G98GUX is sourced from the original manufacturer or authorized distributors?
All 74AUP2G98GUX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G98GUX meets industry standards.
7.What is the process for return or replacement of 74AUP2G98GUX?
All 74AUP2G98GUX units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G98GUX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G98GUX part is unused and in its original packaging.
Return procedure for 74AUP2G98GUX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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