NXP Semiconductors 74AUP2GU04GF,132

Overview

74AUP2GU04GF,132 from Nexperia is a dual unbuffered CMOS inverter optimized for ultra-low-power operation across 0.8 V to 3.6 V supply rails, delivering ICC ≤ 0.9 μA (max) at −40 °C to +125 °C, propagation delay as low as 0.3 ns at VCC = 3.6 V (CL = 5 pF), and overvoltage-tolerant inputs up to 3.6 V - deployed in battery-powered sensor interfaces and crystal oscillator bias networks.

For engineers reviewing the 74AUP2GU04GF,132 datasheet, 74AUP2GU04GF,132 pinout, 74AUP2GU04GF,132 application, or 74AUP2GU04GF,132 equivalent, this device serves as a precision signal inversion element where static power budget, input voltage flexibility, and noise-immune switching are critical selection criteria.

Technical Context

This device implements two independent unbuffered inverter stages using advanced AUP (Advanced Ultra Low Power) CMOS process technology, enabling rail-to-rail input compatibility and output swing with no internal buffering - resulting in minimal propagation delay variation across VCC and temperature. Its unbuffered architecture avoids added stage delay but requires careful load capacitance management (CL ≤ 30 pF) to maintain specified tpd.

Input thresholds scale with VCC (VIH ≥ 0.75 × VCC; VIL ≤ 0.25 × VCC), and output drive strength is graded by supply voltage: VOH ≥ 2.30 V at IO = −4.0 mA and VCC = 3.0 V, while VOL ≤ 0.50 V under same conditions - supporting robust logic-level translation in mixed-voltage subsystems.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (no leads); 6 terminals; body dimensions 1.0 mm × 1.0 mm × 0.35 mm (SOT1202). Pin 1 index located at lower-left corner below marking code 'aD'.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual unbuffered inverter applications.

Compared with SN74LVC2G04DBVR and 74LVC2G04GW,125, the 74AUP2GU04GF,132 delivers superior static power efficiency and input overvoltage resilience - making it the preferred choice for energy-constrained, multi-rail embedded systems where signal fidelity and long-term reliability are prioritized over raw drive capability.

Availability

74AUP2GU04GF,132 is available at Aetrix Electronics and suitable for battery-powered sensor nodes, crystal oscillator circuits, low-voltage logic-level translation, and reset signal conditioning requiring stable component supply across extended temperature ranges.

Supply support for 74AUP2GU04GF,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential system functionality, delivering high-performance, reliable, and efficient components for automotive, industrial, mobile, and computing applications.

The 74AUP2GU04GF,132 belongs to Nexperia's Advanced Ultra Low Power (AUP) logic family, engineered specifically for energy-sensitive applications demanding nanowatt static consumption, wide supply adaptability, and robust noise immunity in space-constrained designs.

FAQ

Can the 74AUP2GU04GF,132 be used as a linear amplifier?

Yes - its unbuffered architecture allows DC biasing into the linear region using external feedback resistors (R1 ≥ 3 kΩ, R2 ≤ 1 MΩ), achieving open-loop gain of 20 and unity-gain bandwidth of 5 MHz. This is documented in Figure 8 of the official datasheet, with output centered at 0.5 × VCC and peak-to-peak swing of VCC − 1.5 V.

What is the maximum capacitive load the 74AUP2GU04GF,132 can drive while maintaining specified propagation delay?

The device is characterized up to CL = 30 pF across all VCC and temperature ranges. At CL = 30 pF and VCC = 3.0–3.6 V, tpd remains ≤ 5.7 ns (−40 °C to +125 °C). Driving loads beyond 30 pF increases delay nonlinearly and may degrade waveform fidelity due to increased slew rate limitations.

Does the 74AUP2GU04GF,132 support partial power-down operation?

No - the device lacks individual channel enable/disable control or power-down mode. However, its ICC ≤ 0.9 μA (max) at full VCC range means it draws negligible current even when actively switching at low frequencies, effectively functioning as a "always-on but near-zero-power" element in sleep-mode subsystems.

How does the input threshold scaling affect noise margin at 1.2 V supply?

At VCC = 1.2 V, VIH ≥ 0.9 V and VIL ≤ 0.3 V, yielding DC noise margins of 0.3 V (high) and 0.3 V (low). Combined with high noise immunity design and <10 % overshoot, this ensures reliable operation in noisy 1.2 V domains such as LPDDR4 PHY interfaces or ultra-low-power MCU peripherals.