Nexperia USA Inc. 74AUP2GU04GS,132

Overview

74AUP2GU04GS,132 from Nexperia is a dual unbuffered CMOS inverter optimized for ultra-low-power operation across 0.8 V to 3.6 V supply rails, delivering ICC ≤ 0.9 μA (max) at −40 °C to +125 °C, propagation delay as low as 0.3 ns at VCC = 3.6 V/CL = 5 pF, and overvoltage-tolerant inputs up to 3.6 V - deployed in battery-powered sensor nodes and low-noise clock conditioning circuits.

For engineers reviewing the 74AUP2GU04GS,132 datasheet, 74AUP2GU04GS,132 pinout, 74AUP2GU04GS,132 application, or 74AUP2GU04GS,132 equivalent, this device serves as a precision signal inversion element where static power budget, input voltage flexibility, and sub-1 ns timing stability under light capacitive loads are critical selection criteria.

Technical Context

This device implements two independent unbuffered inverter stages using advanced AUP (Advanced Ultra-low Power) CMOS technology, eliminating internal buffering to minimize propagation delay and capacitive loading while preserving rail-to-rail logic swing. Each gate operates with symmetrical VIH/VIL thresholds defined as 0.75×VCC and 0.25×VCC respectively.

Its input structure supports overvoltage tolerance up to 3.6 V regardless of VCC level, enabling safe interfacing with higher-voltage logic domains. Dynamic performance is characterized across four load capacitances (5–30 pF) and five VCC ranges, with tpd specified down to 0.3 ns (VCC = 3.0–3.6 V, CL = 5 pF) and CPD = 4.5 pF at 3.6 V.

Key Specifications

Pinout & Package

XSON6 package (SOT1202): extremely thin small outline, no leads, 6-terminal surface-mount device with 1.0 mm × 1.0 mm × 0.35 mm body dimensions and wettable flank terminations for automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual inverter applications.

Compared with SN74LVC2G04DSFR and 74LVC2GU04GW,125, the 74AUP2GU04GS,132 uniquely enables sub-1 V operation with lowest ICC and tightest tpd spec, making it irreplaceable in ultra-low-power, miniaturized, and multi-rail embedded systems where every nanoamp and picosecond matters.

Availability

74AUP2GU04GS,132 is available at Aetrix Electronics and suitable for battery-powered IoT sensors, automotive body control modules, and industrial edge node timing circuits requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP2GU04GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, with leadership in advanced packaging and automotive-qualified components.

The 74AUP2GU04GS,132 belongs to the Advanced Ultra-low Power (AUP) logic family, engineered specifically for energy-constrained applications demanding nanowatt static power, wide-VCC flexibility, and robust noise immunity in compact form factors.

FAQ

Can 74AUP2GU04GS,132 operate reliably at 0.85 V supply?

Yes. The device is fully specified from 0.8 V to 3.6 V, with guaranteed VIH ≥ 0.75×VCC and VIL ≤ 0.25×VCC across the full temperature range (−40 °C to +125 °C). At 0.85 V, VIH is ensured ≥ 0.638 V and VIL ≤ 0.213 V, supporting clean logic transitions with standard AUP-compatible drivers.

Is the 74AUP2GU04GS,132 pin-compatible with other AUP dual inverters in XSON6?

Yes - all Nexperia AUP dual inverters in SOT1202 (XSON6) share identical 1.0×1.0 mm footprint and pinout: Pin 1 = 1A, Pin 2 = GND, Pin 3 = 2A, Pin 4 = 2Y, Pin 5 = VCC, Pin 6 = 1Y. This includes variants like 74AUP2G04 and 74AUP2G14, enabling direct functional substitution without layout change.

What is the maximum capacitive load this device can drive while maintaining 0.5 ns propagation delay?

At VCC = 3.3 V, the device achieves tpd ≤ 0.5 ns only with CL ≤ 5 pF (per Table 8). With CL = 10 pF, tpd increases to ≤ 0.7 ns; at CL = 15 pF, it rises to ≤ 0.9 ns. For sub-0.5 ns timing, keep total load (including trace, probe, and input capacitance) below 5 pF using short, guarded routing.

Does the 74AUP2GU04GS,132 support partial power-down (Ioff) protection?

No. This device does not implement Ioff - when VCC = 0 V, inputs and outputs are not high-impedance and may draw leakage current if driven externally. For true Ioff behavior, consider Nexperia's 74LVC2G04 variants (e.g., 74LVC2G04DP), which specify Ioff ≤ 10 μA at VCC = 0 V and VI = 0–3.6 V.