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Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

NXP Semiconductors 74AUP2T1326GF,115

Name: 74AUP2T1326GF,115
Brand: NXP Semiconductors
SKU: 74AUP2T1326GF,115
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74AUP2T1326GF,115

Manufacturer:: NXP Semiconductors

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 10-XFDFN

Datasheet:: 74AUP2T1326GF,115.pdf

Description:: IC BUFFER NON-INVERT 3.6V 10XSON

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Product details

Overview

74AUP2T1326GF,115 from Nexperia is a dual-supply, low-power, dual buffer/line driver with independent 3-state control and logic-level translation capability. It integrates OR-gated output enable (1Y) and two Schmitt-trigger OE inputs (1OE, 2OE), supports VCC(A)/VCC(B) from 1.1 V to 3.6 V independently, delivers propagation delays as low as 1.3 ns (VCC = 2.3–2.7 V), and operates across −40 °C to +85 °C for mixed-voltage I/O interfacing in portable and battery-powered systems.

For engineers reviewing the 74AUP2T1326GF,115 datasheet, 74AUP2T1326GF,115 pinout, 74AUP2T1326GF,115 application, or 74AUP2T1326GF,115 equivalent, this device is selected for precise voltage-domain bridging where low ICC (≤0.9 µA), IOFF-enabled partial power-down, and hysteresis-enabled noise immunity on enable lines are critical design requirements.

Technical Context

The device implements dual independent buffer paths: input A drives outputs 2Y and 3Y under control of 1OE and 2OE respectively, while 1Y is the logical OR of both OE signals referenced to VCC(A). Its Schmitt-trigger OE inputs provide ≥0.27 V hysteresis (VH) at 1.65 V VCC(A), enabling clean signal recovery from slow-rising or noisy control lines.

VCC(A) powers pins 1OE, 2OE, and 1Y; VCC(B) powers A, 2Y, and 3Y; GND is common. The IOFF circuit blocks backflow current when either supply is powered down, satisfying JEDEC JESD78 Class II latch-up robustness (>100 mA) and supporting hot-swap and power sequencing in multi-rail systems.

Key Specifications

Parameter	Value and Actual Design Meaning
VCC Range	1.1 V to 3.6 V per supply (VCC(A) and VCC(B) independently set)
ICC Max	0.9 µA - enables ultra-low static power in always-on subsystems
tpd Min	1.3 ns - ensures sub-nanosecond timing margin for high-speed interface bridging
VH (Hysteresis)	0.27 V min at 1.65 V VCC(A) - rejects >270 mV of input noise on enable lines
IOFF Leakage	±0.5 µA max - prevents damaging back-current during partial power-down
Operating Temp	−40 °C to +85 °C - qualified for industrial and extended-temperature embedded use
ESD HBM	2000 V - exceeds JEDEC Class 2A for board-level handling robustness

Pinout & Package

XSON10 (SOT1081-2) package: 1.0 mm × 1.7 mm × 0.5 mm body, no leads, 10-terminal plastic extremely thin small outline package with exposed pad not present.

Pin/Terminal	Circuit Role	Design Meaning
1 (3Y)	Data output B	Active-high buffered output driven by A, enabled by 2OE (VCC(B)-referenced)
2 (VCC(B))	Supply B	Power rail for outputs 2Y/3Y and input A; sets VOH/VOL thresholds
3 (A)	Data input	VCC(B)-referenced input accepting up to 3.6 V; drives both 2Y and 3Y
4 (VCC(A))	Supply A	Power rail for 1OE, 2OE, and 1Y; defines Schmitt thresholds and OR logic
5 (GND)	Ground	Common reference for all supplies and I/O; required for IOFF and ESD path
6 (1OE)	Output enable A	Schmitt-trigger input (VCC(A)-referenced); LOW disables 2Y
7 (2OE)	Output enable B	Schmitt-trigger input (VCC(A)-referenced); LOW disables 3Y
8 (1Y)	OR output	High-impedance when both 1OE and 2OE are HIGH; otherwise logic OR result
9 (2Y)	Data output B	Active-high buffered output driven by A, enabled by 1OE (VCC(B)-referenced)
10 (n.c.)	No connect	Internally unconnected terminal; must remain floating or grounded per layout rules

Key Features

Feature	Design Value
Dual independent supply domains	VCC(A) and VCC(B) each configurable 1.1–3.6 V for flexible voltage translation
Schmitt-trigger OE inputs	VT+ and VT− thresholds differ by ≥0.27 V to eliminate chatter on slow/noisy control lines
IOFF partial power-down	Blocks reverse current flow when either VCC is 0 V, enabling safe multi-rail sequencing
Ultra-low ICC	0.9 µA max ensures <1 µW static power at 1.8 V, critical for battery longevity
JEDEC-compliant interfaces	Validated per JESD8-7 (1.2–1.95 V), JESD8-5 (1.8–2.7 V), JESD8-B (2.7–3.6 V)

Applications

Mobile Baseband Interface

Industrial Sensor Hub

Use Scenario: Bridging GPIOs between 1.8 V application processor and 3.3 V sensor array with independent enable control.

IC Role / Device Role / Timing Role: Dual-supply buffer translating logic levels while isolating power domains and enabling/disabling individual sensor channels.

Use Value: Eliminates level-shifter IC count; Schmitt OE inputs suppress noise from long PCB traces; IOFF prevents backfeed during processor sleep mode.

Use Scenario: Interfacing multiple analog sensor ADCs (2.5 V) to a 1.2 V microcontroller I/O bank with shared enable signaling.

IC Role / Device Role / Timing Role: Voltage-domain translator and channel-selectable driver with OR'd enable for coordinated wake-up signaling.

Use Value: Enables single 1.2 V MCU to manage heterogeneous 2.5 V sensors; 1.3 ns tpd preserves timing integrity in sampled-data systems.

Wearable Power Management

IoT Edge Node

Use Scenario: Controlling 1.5 V PMIC enable lines from a 3.3 V battery gauge IC with glitch-free assertion.

IC Role / Device Role / Timing Role: Low-power buffer with hysteresis on OE to convert noisy battery voltage monitor output into clean enable pulses.

Use Value: Prevents false PMIC toggling due to battery ripple; 0.9 µA ICC extends coin-cell life beyond 10 years in standby.

Use Scenario: Isolating BLE SoC (1.8 V I/O) from legacy 2.7 V wireless transceiver while supporting hot-plug detection.

IC Role / Device Role / Timing Role: Bidirectional domain bridge with IOFF protection during transceiver insertion/removal events.

Use Value: Avoids bus contention and latch-up during field maintenance; JEDEC JESD8-5 compliance ensures interoperability.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-supply buffer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC2T45DCUR	Auto-direction sensing; no Schmitt OE; higher ICC (10 µA typ); 3.6 V max VCC	Requires external direction control logic; unsuitable for slow/noisy OE signals	Select only if bidirectional data flow is needed and OE noise immunity is non-critical
74LVC2T45DP,122	Same pinout; lacks IOFF; lower hysteresis (0.1 V typ); 1.65–5.5 V VCC range	Cannot safely power-down one rail while other remains active; higher ESD risk (1500 V HBM)	Acceptable only in fixed-rail, non-hot-swap designs with clean enable sources

Compared with SN74LVC2T45DCUR and 74LVC2T45DP,122, the 74AUP2T1326GF,115 uniquely combines Schmitt-trigger OE inputs, IOFF protection, and sub-1 µA ICC-making it the sole choice for battery-constrained, multi-rail, noise-prone embedded interfaces requiring guaranteed power-down safety and enable-line noise rejection.

Availability

74AUP2T1326GF,115 is available at Aetrix Electronics and suitable for mobile baseband interface, industrial sensor hub, wearable power management, and IoT edge node applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for 74AUP2T1326GF,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in consumer, industrial, and communications markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and energy-sensitive applications, emphasizing sub-microamp ICC, dual-supply flexibility, and robust IOFF behavior for modern multi-voltage system architectures.

FAQ

What is the maximum allowable voltage difference between VCC(A) and VCC(B)?

The datasheet does not specify a maximum differential voltage limit. Both supplies are rated independently from −0.5 V to +4.6 V absolute, and operation is validated across the full 1.1 V to 3.6 V range for each. As long as each supply remains within its absolute maximum ratings and recommended operating conditions, any combination-including VCC(A) = 1.2 V and VCC(B) = 3.3 V-is fully supported and characterized.

Can 1Y be used as a dedicated enable-status indicator for both 2Y and 3Y?

Yes. Pin 1Y outputs HIGH when either 1OE or 2OE is LOW (per function table), and goes HIGH-Z only when both OE inputs are HIGH. This provides real-time visibility into the combined enable state of both output channels without external logic, simplifying system-level status monitoring in space-constrained designs.

Does the device support hot-swapping of VCC(B) while VCC(A) remains powered?

Yes. The IOFF circuit actively disables outputs 2Y and 3Y when VCC(B) drops below ~0.2 V, preventing back-current from VCC(A)-powered inputs or 1Y into the unpowered VCC(B) domain. This behavior is explicitly characterized in Table 7 (IOFF leakage), ensuring safe hot-swap operation in modular or field-replaceable subsystems.

Are the Schmitt-trigger thresholds (VT+, VT−) affected by temperature or supply variation?

Yes. VT+ and VT− scale with VCC(A): at 1.65 V VCC(A), VT+ is 0.91–1.29 V and VT− is 0.47–0.84 V; at 2.3 V VCC(A), VT+ is 1.37–1.77 V and VT− is 0.69–1.04 V. Full min/max values across −40 °C to +85 °C are provided in Table 11, confirming hysteresis (VH) remains ≥0.27 V over temperature and voltage.

74AUP2T1326GF,115 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: 74AUP

Package/Case:: 10-XFDFN

Packaging:: Bulk

Product Status:: Active

Logic Type:: Buffer, Non-Inverting

Number of Elements:: 2

Number of Bits per Element:: 1

Input Type:: -

Output Type:: 3-State

Current - Output High, Low:: 4mA, 4mA

Voltage - Supply:: 1.1V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 10-XSON (1.7x1)

74AUP2T1326GF,115 FAQ

1.How can I place an order for 74AUP2T1326GF,115 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP2T1326GF,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP2T1326GF,115 reliable?

The price and inventory of 74AUP2T1326GF,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2T1326GF,115 is usually 5 days.

3.What payment methods are accepted for 74AUP2T1326GF,115?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2T1326GF,115 transactions.

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4.How is shipping managed for 74AUP2T1326GF,115?

74AUP2T1326GF,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP2T1326GF,115 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP2T1326GF,115?

For technical support, including 74AUP2T1326GF,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2T1326GF,115 requirements.

6.How does Aetrix verify that 74AUP2T1326GF,115 is sourced from the original manufacturer or authorized distributors?

All 74AUP2T1326GF,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2T1326GF,115 meets industry standards.

7.What is the process for return or replacement of 74AUP2T1326GF,115?

All 74AUP2T1326GF,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2T1326GF,115, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP2T1326GF,115 part is unused and in its original packaging.

Return procedure for 74AUP2T1326GF,115:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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