Nexperia USA Inc. 74AUP2T1326GF,132

Overview

74AUP2T1326GF,132 from Nexperia is a dual-supply, low-power, dual buffer/line driver with independent 3-state control and logic-level translation capability. It integrates OR-gated output enable (1Y) and two Schmitt-trigger OE inputs (1OE, 2OE), supports VCC(A)/VCC(B) from 1.1 V to 3.6 V independently, delivers propagation delays as low as 1.3 ns (VCC = 2.3–2.7 V), and operates across −40 °C to +85 °C for mixed-voltage I/O interfacing in portable and battery-powered systems.

For engineers reviewing the 74AUP2T1326GF,132 datasheet, 74AUP2T1326GF,132 pinout, 74AUP2T1326GF,132 application, or 74AUP2T1326GF,132 equivalent, this device serves as a voltage-translation buffer for FPGA-to-ASIC interconnects, multi-rail sensor hubs, and low-noise power management sequencers where IOFF-enabled partial power-down and hysteresis noise immunity are critical design requirements.

Technical Context

The device implements dual-domain logic buffering: input A and outputs 2Y/3Y reference VCC(B), while 1OE, 2OE, and 1Y reference VCC(A). Its Schmitt-trigger OE inputs provide ≥0.27 V hysteresis (VH) at 1.65 V VCC(A), enabling clean edge regeneration of slow or noisy control signals. The OR-combined 1Y output ensures synchronized enable signaling across both output channels.

IOFF circuitry actively disables all outputs when either VCC(A) or VCC(B) is powered down, blocking backflow current up to ±0.5 µA. Static supply current is limited to 0.9 µA max per rail, and dynamic power dissipation is governed by CPD = 3.0–3.6 pF per active output, supporting ultra-low-power operation in always-on subsystems.

Key Specifications

Pinout & Package

XSON10 (SOT1081-2) package: plastic extremely thin small outline, no leads, 10-terminal, body size 1.0 × 1.7 × 0.5 mm. Pin 1 indicator located on lower-left corner below marking code.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-supply buffer applications.

Compared with SN74AVCH2T245RSWR and 74LVC2T45DP,125, the 74AUP2T1326GF,132 uniquely combines Schmitt-trigger OE inputs, IOFF protection, and sub-1.5 ns propagation delay - making it the only option among the three that guarantees noise-immune enable control and safe partial power-down in mixed-rail portable systems.

Availability

74AUP2T1326GF,132 is available at Aetrix Electronics and suitable for portable sensor hubs, FPGA-to-MCU interfaces, and industrial I/O modules requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for 74AUP2T1326GF,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance logic, analog, and discrete components, with leadership in energy-efficient and reliable solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra Low Power) product line targets battery-constrained and thermally sensitive applications, delivering sub-1 µA static current and robust noise immunity through Schmitt-trigger inputs and IOFF architecture.

FAQ

What is the maximum allowable voltage on input A when VCC(B) = 0 V?

Input A tolerates up to 3.6 V regardless of VCC(B) state, per datasheet Section 9 (Recommended Operating Conditions) and Table 5 (Limiting Values). This allows safe "hot insertion" of signals into unpowered domains. The internal clamping diodes limit IIK to −50 mA, and IOFF blocks backflow, ensuring no damage occurs even during VCC(B) ramp-up sequences.

Can 1OE and 2OE be tied together to simplify control logic?

Yes - tying 1OE and 2OE together enables simultaneous 3-state control of both 2Y and 3Y outputs, while 1Y remains active-high (LOW on either OE forces 1Y HIGH). This configuration preserves the OR function but sacrifices independent channel gating. Ensure the combined OE net capacitance stays within 10 pF to maintain specified enable/disable times (≤10.5 ns).

Does the device support mixed-voltage operation with VCC(A) = 1.8 V and VCC(B) = 3.3 V?

Yes - the datasheet explicitly permits independent VCC(A) and VCC(B) settings across 1.1–3.6 V. At VCC(A) = 1.8 V and VCC(B) = 3.3 V, VIH/VIL thresholds scale correctly (VIH ≈ 1.26 V, VIL ≈ 0.54 V), and VOH/VOL meet 3.3 V logic levels (VOH ≥ 3.2 V, VOL ≤ 0.4 V @ 4 mA), enabling seamless 1.8 V controller-to-3.3 V peripheral interfacing.

How does the IOFF feature behave when only VCC(A) is powered?

When VCC(A) = nominal and VCC(B) = 0 V, IOFF disables A, 2Y, and 3Y outputs, limiting leakage to ±0.5 µA (Table 7). 1Y remains functional since it references VCC(A), allowing status signaling even when the B-rail is off. This asymmetric behavior supports hierarchical power sequencing where control logic remains active while data paths are shut down.