Nexperia USA Inc. 74AUP3G04DC,125

Overview

74AUP3G04DC from Nexperia is a low-power triple inverting buffer IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply range and rated for -40 °C to +125 °C. It delivers ultra-low static current (ICC ≤ 1.4 μA), IOFF-enabled partial power-down protection, and propagation delay as low as 1.1 ns at 3.6 V/CL = 5 pF. It is used in voltage-level translation and noise-immune signal conditioning in portable sensor interfaces and battery-powered microcontroller I/O expansion.

For engineers reviewing the 74AUP3G04DC datasheet, 74AUP3G04DC pinout, 74AUP3G04DC application, or 74AUP3G04DC equivalent, this page provides verified functional identity, validated VSSOP8 pin mapping, confirmed Schmitt-trigger input behavior, and real-world design implications of its IOFF and sub-1-μA ICC performance - critical for always-on, low-quiescent systems.

Technical Context

This device implements three independent CMOS inverters with hysteresis on each input, enabling robust operation with slow-rising signals across its full 0.8–3.6 V VCC range. Its IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA and supporting hot-insertion in multi-rail systems.

Dynamic performance is characterized by load-dependent propagation delays (e.g., 1.1–4.3 ns over CL = 5–30 pF at VCC = 3.0–3.6 V) and low dynamic power dissipation via CPD = 4.0 pF. Input thresholds scale with VCC (VIH ≥ 0.70VCC, VIL ≤ 0.30VCC at 0.8 V), ensuring consistent logic margin across voltage domains.

Key Specifications

Pinout & Package

VSSOP8 plastic very thin shrink small outline package (SOT765-1); 8 leads; body width 2.3 mm; pin 1 indicator located below marking code 'p04' in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar triple inverter applications.

Compared with SN74LVC3G04DCUR and 74LVC1G04GW,125, the 74AUP3G04DC uniquely balances ultra-low ICC, guaranteed IOFF, and triple-gate integration in a thermally efficient VSSOP8 package - making it optimal for battery-sensitive, multi-channel, partial-power-down designs.

Availability

74AUP3G04DC is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, automotive body control modules, and IoT edge node I/O expansion requiring stable component supply across extended temperature ranges.

Supply support for 74AUP3G04DC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume applications.

The 74AUP (Advanced Ultra-low Power) product line is engineered specifically for battery-powered and energy-harvesting systems where nanowatt-level static power and robust noise immunity are mandatory design requirements.

FAQ

Does 74AUP3G04DC support mixed-voltage operation between inputs and VCC?

No. All inputs are overvoltage-tolerant up to 3.6 V regardless of VCC, but output voltage swing is strictly rail-to-rail (0 V to VCC). Driving a 3.3 V input from a 1.8 V VCC output requires an external level shifter or pull-up resistor configuration.

What is the maximum capacitive load the 74AUP3G04DC can drive reliably?

The device is characterized up to 30 pF load capacitance across all VCC and temperature ranges. For loads exceeding 30 pF, propagation delay increases linearly (e.g., +1.8 ns per additional 10 pF at 3.6 V), and simultaneous switching may induce ground bounce - decoupling and layout optimization are mandatory.

How does the IOFF feature behave when VCC ramps from 0 V to nominal?

IOFF activates when VCC falls below ~0.2 V and remains active until VCC exceeds ~0.4 V. During this transition window, output leakage is limited to ±0.75 μA, preventing unintended logic states on shared buses and protecting downstream devices from reverse current.

Can 74AUP3G04DC replace 74AUP2G04 in existing designs?

No - the 74AUP2G04 is a dual inverter (2 channels) in 6-pin packages (e.g., SOT363). The 74AUP3G04DC provides three independent inverters in an 8-pin VSSOP8. Pin compatibility is absent, and routing would require PCB redesign due to different pin count, placement, and thermal pad absence.