My Inquiry
My Account
NXP Semiconductors 74AUP3G04GN,115
- Part No.:
- 74AUP3G04GN,115
- Manufacturer:
- NXP Semiconductors
- Category:
- Gates and Inverters
- Package:
- 8-XFDFN
- Datasheet:
-
74AUP3G04GN,115.pdf
- Description:
- IC INVERTER 3CH 3-INP 8XSON
- Quantity:
- Payment:
- Shipping:
Inventory:95,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AUP3G04GN,115 from Nexperia is a low-power triple inverter IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply voltage, delivering <0.9 μA max ICC at 125 °C, IOFF-enabled partial power-down protection, and propagation delay as low as 1.1 ns (VCC = 3.3 V, CL = 5 pF). It serves as a noise-immune signal conditioning and level-shifting buffer in battery-powered sensor interfaces and portable logic subsystems.
For engineers reviewing the 74AUP3G04GN,115 datasheet, 74AUP3G04GN,115 pinout, 74AUP3G04GN,115 application, or 74AUP3G04GN,115 equivalent, this device is selected for ultra-low static power, wide-voltage compatibility in mixed-supply systems, robust input tolerance up to 3.6 V, and guaranteed operation from –40 °C to +125 °C in space-constrained industrial and automotive-adjacent control modules.
Technical Context
The 74AUP3G04GN,115 implements three independent inverting buffers with Schmitt-trigger input thresholds-VIH ≥ 0.65VCC and VIL ≤ 0.35VCC across 0.9–1.95 V VCC-to reject slow-rising noise on I²C pull-up lines or mechanical switch inputs. Its IOFF circuit actively disables outputs during power-down, limiting backflow current to ±0.75 μA when VCC = 0 V.
Dynamic performance is load- and voltage-dependent: tPD ranges from 1.1 ns (3.3 V, 5 pF) to 6.9 ns (0.8 V, 30 pF), while CPD remains stable at 4.0 pF (3.0–3.6 V), enabling predictable dynamic power calculation via PD = CPD × VCC² × fi × N.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max ICC (Tamb = 125 °C) | 0.9 μA - enables multi-year battery life in always-on wake-up circuits and IoT endpoint sensors. |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - prevents damaging back-current into powered downstream rails during hot-swap or partial system shutdown. |
| Propagation Delay (3.3 V, 5 pF) | 1.1 ns (min) to 4.3 ns (max) - sufficient for 100+ MHz clock distribution in non-critical timing paths. |
| Input Voltage Tolerance | 0 V to 3.6 V - allows interfacing with higher-voltage peripherals (e.g., 3.3 V GPIO) while powered from 1.8 V. |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood automotive ECUs, industrial motor drives, and outdoor edge nodes. |
| ESD Robustness | HBM >5000 V, CDM >1000 V - reduces need for external ESD protection in handheld and field-deployable equipment. |
Pinout & Package
XSON8 package (SOT1116): extremely thin small outline, no leads, 8-terminal surface-mount device measuring 1.2 mm × 1.0 mm × 0.35 mm body height - optimized for high-density PCB layouts in wearables and compact controllers.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 3A (input) | Third inverter input; accepts 0–3.6 V signals regardless of VCC; Schmitt-triggered for noise margin. |
| 2 | 3Y (output) | Inverted output of third gate; drives capacitive loads up to 30 pF with sub-7 ns delay at 3.3 V. |
| 3 | 1Y (output) | Inverted output of first gate; electrically isolated from other outputs; supports independent loading. |
| 4 | GND | Dedicated ground reference; must be low-impedance connection to minimize switching noise coupling. |
| 5 | 2Y (output) | Inverted output of second gate; shares same VCC/GND net but has separate output path for fanout isolation. |
| 6 | 2A (input) | Second inverter input; identical electrical behavior to Pin 1 and Pin 7; enables three independent logic inversions. |
| 7 | 1A (input) | First inverter input; pin 1 index located below marking "p4" in lower-left corner per Fig. 5. |
| 8 | VCC | Single supply rail; decoupling capacitor (100 nF) required within 2 mm for stable high-speed operation. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Provides >0.3VCC hysteresis across full VCC range, eliminating contact bounce and EMI-induced glitches on pushbutton or encoder inputs. |
| IOFF partial power-down | Disables all outputs when VCC = 0 V, preventing reverse current flow into powered subsystems during firmware-initiated sleep modes. |
| Ultra-low ICC | ≤1.4 μA max over –40 °C to +125 °C ensures negligible quiescent drain in always-on monitoring circuits (e.g., tamper detection). |
| Wide-VCC JEDEC compliance | Validated to JESD8-12 through JESD8-B standards - guarantees interoperability with legacy and next-gen low-voltage ASICs/FPGAs. |
| High noise immunity | Input noise margin ≥30% of VCC at 1.8 V and ≥25% at 3.3 V - suppresses crosstalk in dense routing environments like display driver PCBs. |
Applications
| Industrial Sensor Interface | Portable Device Power Sequencing |
|---|---|
|
Use Scenario: Signal conditioning for analog sensor outputs feeding ADCs in programmable logic controllers. IC Role / Device Role / Timing Role: Inverts and cleans noisy open-collector sensor alerts before latching into microcontroller GPIOs. Use Value: Schmitt-trigger inputs reject 100 ns–1 μs transients from 24 V solenoid switching, reducing false triggers by >95% vs. standard inverters. |
Use Scenario: Controlled enable/disable sequencing of multiple LDOs in battery-powered medical monitors. IC Role / Device Role / Timing Role: Generates synchronized inverted enable signals for cascaded power rails during cold start and shutdown. Use Value: IOFF function isolates downstream LDOs during main rail collapse, preventing latch-up and ensuring deterministic reset behavior. |
| Automotive Body Control Module | IoT Edge Node Wake-Up Logic |
|
Use Scenario: Debouncing and inversion of door-lock switch inputs in non-safety-critical BCMs. IC Role / Device Role / Timing Role: Provides glitch-free digital input conditioning prior to CAN transceiver interrupt generation. Use Value: Guaranteed operation at 125 °C ambient enables placement near engine bay electronics without derating or heatsinking. |
Use Scenario: Low-power wake-up signal generation from motion or environmental sensors in asset trackers. IC Role / Device Role / Timing Role: Inverts interrupt pulses from MEMS accelerometers to match active-low MCU wake pin polarity. Use Value: 0.9 μA max ICC extends coin-cell battery life to >5 years in periodic-scan configurations (1 Hz sampling). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC3G04DCUR | Higher ICC (10 μA typ), no IOFF, 1.65–5.5 V VCC range, SOT23-8 package (larger footprint) | Not suitable for partial power-down systems; requires external isolation for hot-swap scenarios | Select only if 5 V tolerance or legacy SOT23 assembly is mandatory; avoid where ultra-low ICC or IOFF is required. |
| 74LVC3G04GM,132 | Same XSON8 footprint (SOT902-2), but rated only to +85 °C and lacks IOFF circuitry | Cannot be used in under-hood or high-ambient industrial enclosures requiring 125 °C operation | Acceptable for consumer-grade wearables or indoor gateways; not recommended for automotive-adjacent or extended-temp deployments. |
Compared with SN74LVC3G04DCUR and 74LVC3G04GM,132, the 74AUP3G04GN,115 uniquely combines sub-μA static current, IOFF-enabled power-domain isolation, and full –40 °C to +125 °C qualification in a 1.2 × 1.0 mm XSON8 package-making it the only choice for thermally constrained, battery-sensitive, and mixed-rail industrial designs.
Availability
74AUP3G04GN,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable device power sequencing, automotive body control modules, and IoT edge node wake-up logic requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP3G04GN,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions with industry-leading reliability and energy efficiency.
The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications-designed specifically for ultra-low ICC, wide-VCC compatibility, and robust IOFF behavior in portable, industrial, and automotive-adjacent electronics.
FAQ
Does the 74AUP3G04GN,115 support true bidirectional signal translation?
No. It is a unidirectional inverter only: inputs accept 0–3.6 V signals regardless of VCC, but outputs swing rail-to-rail between GND and VCC. It cannot translate signals from a higher-voltage domain to a lower one without external biasing or level-shifter circuitry.
What is the maximum capacitive load the 74AUP3G04GN,115 can drive reliably?
The device is characterized up to 30 pF load capacitance (Table 8), with tPD increasing predictably from 1.1 ns (5 pF) to 6.9 ns (30 pF) at 3.3 V. Driving >30 pF may cause excessive rise/fall times or output overshoot; add series termination or buffer stages beyond this limit.
Can the 74AUP3G04GN,115 be operated at 0.7 V supply?
No. The absolute minimum recommended VCC is 0.8 V per Table 6. Operation below 0.8 V risks undefined logic states, increased propagation delay variability, and failure to meet VIH/VIL thresholds-potentially causing metastability or functional failure.
Is the marking code "p4" unique to the 74AUP3G04GN,115 variant?
Yes. Per Table 2, "p4" identifies the GN variant (SOT1116/XSON8, 1.2 × 1.0 mm); the DC (VSSOP8) and GT (SOT833-1) variants use "p04", confirming package-specific traceability and distinguishing GN's thinner 0.35 mm profile for ultra-dense layouts.
74AUP3G04GN,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Inverter
- Number of Circuits:
- 3
- Number of Inputs:
- 3
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 5.4ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON (1.2x1)
74AUP3G04GN,115 FAQ
1.How can I place an order for 74AUP3G04GN,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP3G04GN,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP3G04GN,115 reliable?
The price and inventory of 74AUP3G04GN,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP3G04GN,115 is usually 5 days.
3.What payment methods are accepted for 74AUP3G04GN,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP3G04GN,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP3G04GN,115?
74AUP3G04GN,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP3G04GN,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP3G04GN,115?
For technical support, including 74AUP3G04GN,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP3G04GN,115 requirements.
6.How does Aetrix verify that 74AUP3G04GN,115 is sourced from the original manufacturer or authorized distributors?
All 74AUP3G04GN,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP3G04GN,115 meets industry standards.
7.What is the process for return or replacement of 74AUP3G04GN,115?
All 74AUP3G04GN,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP3G04GN,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP3G04GN,115 part is unused and in its original packaging.
Return procedure for 74AUP3G04GN,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP3G04GN,115 Tags
-
SN74LVC1G14DBVR
Texas Instruments
-
SN74LVC1G14DCKR
Texas Instruments
-
SN74AHC1G14DBVR
Texas Instruments
-
SN74LVC1G08DBVR
Texas Instruments
-
SN74LVC1G08DCKR
Texas Instruments
-
SN74LVC1G32DCKR
Texas Instruments
-
SN74LVC1G04DBVR
Texas Instruments
.jpg)
-
74LVC1G08GW,125
Nexperia USA Inc.
-
SN74LVC1G04DCKR
Texas Instruments
-
SN74AHC1G08DBVR
Texas Instruments
-
SN74LVC1G32DBVR
Texas Instruments
-
SN74AHCT1G08DBVR
Texas Instruments
Tech Hub
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
LDO regulator guide covering low dropout voltage, power dissipation, thermal design, PSRR, output noise, capacitor stability, adjustable LDO circuits, LDO vs buck converter and datasheet selection chec…
Conditional Access Module guide covering CAM meaning, CI/CI+ interface, smart card authorization, DVB security workflow, TV and set-top box compatibility, internal electronics, ESD protection, connecto…
Guide to electronic component obsolescence covering EOL risk, PCN/PDN notices, last-time buy planning, replacement options, form-fit-function validation, counterfeit risk and BOM lifecycle management.
18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…
Hall effect sensor guide covering working principle, linear and digital sensors, Arduino circuits, current sensing, speed detection, automotive applications, A3144 examples, signal filtering and datash…
