Nexperia USA Inc. 74AUP3G04GT,115

Overview

74AUP3G04GT,115 from Nexperia is a triple unbuffered inverter IC in a 8-pin XSON package, operating from 0.8 V to 3.6 V supply, with typical propagation delay of 2.3 ns at 3.3 V and 30 pF load, used for logic-level signal inversion in ultra-low-power portable interfaces.

For engineers reviewing the 74AUP3G04GT,115 datasheet, 74AUP3G04GT,115 pinout, 74AUP3G04GT,115 application, or 74AUP3G04GT,115 equivalent, key selection factors include its rail-to-rail input compatibility, sub-1 µA static current at 25 °C, and guaranteed operation down to 0.8 V for battery-powered sensor nodes and wearables.

Technical Context

This device implements three independent CMOS inverters in a single die, each with Schmitt-trigger inputs omitted-ensuring clean digital inversion without hysteresis. It supports I_OFF partial power-down mode, preventing backflow current when V_CC = 0 V.

The AUP (Advanced Ultra-low Power) family targets sub-1-V operation with optimized drive strength (±4 mA at V_CC = 3.3 V), enabling direct interfacing with 1.2-V and 1.8-V logic domains while maintaining noise margins above 0.3×V_CC.

Key Specifications

Pinout & Package

Package: 8-pin XSON (2 × 1.25 mm, 0.5 mm pitch), leadless, moisture sensitivity level MSL3, JEDEC-compliant footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar unbuffered inverter applications.

Compared with SN74LVC3G04DCUR and 74LVC1G04GW,125, the 74AUP3G04GT,115 uniquely supports sub-1-V operation with I_OFF protection-making it the sole option for energy-constrained, hot-pluggable, or multi-rail sensor subsystems requiring integrated triple inversion.

Availability

74AUP3G04GT,115 is available at Aetrix Electronics and suitable for wearable health monitors, IoT edge nodes, and smart meter interfaces requiring stable component supply across extended product lifecycles.

Supply support for 74AUP3G04GT,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The AUP family was engineered specifically for ultra-low-voltage, ultra-low-power portable electronics-prioritizing sub-1-V functionality, nanowatt static consumption, and compact packaging without sacrificing speed or noise immunity.

FAQ

What is the maximum recommended capacitive load for 74AUP3G04GT,115?

The device is characterized up to 50 pF per output, with propagation delay increasing linearly beyond 30 pF. Driving >50 pF may cause marginal timing at 3.3 V and exceed 5 ns t_PD; for loads >50 pF, add series termination or buffer stage to maintain signal integrity.

Does 74AUP3G04GT,115 support mixed-voltage I/O?

No-it does not support true mixed-voltage I/O. All inputs and outputs are referenced to the single V_CC rail. Inputs accept 0–V_CC voltages, but output swing is bounded by V_CC and GND; level translation requires external circuitry or a dedicated translator IC.

Can 74AUP3G04GT,115 be used in I²C bus pull-up paths?

No. Its outputs are push-pull, not open-drain, and lack bus arbitration capability. Using it in I²C pull-up paths would short SDA/SCL lines during low output states. Dedicated I²C level translators like PCA9306 are required for voltage domain bridging.

Is thermal derating required for continuous operation at 3.6 V?

No thermal derating is needed below 85 °C ambient. At 3.6 V and 25 °C, total power dissipation remains <15 µW per inverter (I_CC × V_CC). Junction temperature rise is negligible (<0.1 °C/W) in standard FR-4 layouts with minimal copper pour.