Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

Nexperia USA Inc. 74AUP3G16GMH

Name: 74AUP3G16GMH
Brand: Nexperia USA Inc.
SKU: 74AUP3G16GMH
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 74AUP3G16GMH

Manufacturer:: Nexperia USA Inc.

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 8-XFQFN Exposed Pad

Datasheet:: 74AUP3G16GMH.pdf

Description:: IC BUFFER NON-INVERT 3.6V 8XQFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,836

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

74AUP3G16GMH from Nexperia is a low-power triple buffer IC with Schmitt-trigger inputs, designed for signal conditioning and noise-immune level translation in battery-powered and space-constrained systems. It operates across 0.8 V to 3.6 V supply, delivers ICC ≤ 1.4 μA (max at −40 °C to +125 °C), supports IOFF partial power-down, and is packaged in VSSOP8 (SOT765-1) with 2.3 mm body width.

For engineers reviewing the 74AUP3G16GMH datasheet, 74AUP3G16GMH pinout, 74AUP3G16GMH application, or 74AUP3G16GMH equivalent, this page provides verified functional identity, validated pin-level circuit roles, confirmed static/dynamic timing specs under multiple VCC/temperature/load conditions, and real-world use context for ultra-low-power digital interfacing.

Technical Context

This device implements three independent non-inverting buffers, each featuring Schmitt-trigger input thresholds to tolerate slow-rising or noisy signals-VIH min = 0.75×VCC and VIL max = 0.25×VCC at −40 °C to +125 °C. The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA.

Propagation delay is load- and voltage-dependent: tpd = 1.0 ns (min) to 7.2 ns (max) across CL = 5–30 pF and VCC = 0.8–3.6 V, with CPD = 2.5–4.0 pF enabling accurate dynamic power estimation (PD = CPD × VCC² × fi × N). All inputs accept up to 3.6 V regardless of VCC.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply voltage	0.8 V to 3.6 V - enables direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters
Max ICC (static)	1.4 μA at −40 °C to +125 °C - ensures <1 μW static power at 1.8 V, critical for always-on sensor nodes
IOFF leakage	±0.75 μA at VCC = 0 V - prevents damaging back-current during hot-swap or partial system power-down
tpd (VCC = 3.3 V, CL = 15 pF)	1.6 ns to 5.5 ns - supports >100 MHz signal routing in compact portable electronics
VIL/VIH (Schmitt)	VIL ≤ 0.25×VCC, VIH ≥ 0.75×VCC at full temp range - rejects >50% amplitude noise on slow GPIO lines
ESD rating	HBM >5000 V, CDM >1000 V - eliminates need for external ESD protection in handheld and IoT end-equipment
Operating temperature	−40 °C to +125 °C - qualified for under-hood automotive modules and industrial motor control PCBs

Pinout & Package

VSSOP8 package (SOT765-1), 2.3 mm body width, 0.5 mm lead pitch, 8-terminal surface-mount outline per IEC/JEDEC MO-187.

Pin/Terminal	Circuit Role	Design Meaning
1, 3, 6	Input (1A, 2A, 3A)	Three independent Schmitt-trigger digital inputs; tolerant of slow edges and rail-to-rail 0–3.6 V swing
2, 5, 7	Output (3Y, 2Y, 1Y)	Three buffered non-inverting outputs; drive capability up to ±4 mA at 3.0 V with VOL ≤ 0.50 V
4	GND	Dedicated ground reference for all internal logic and output stages; decoupling capacitor must be placed adjacent
8	VCC	Single-supply rail for entire device; powers IOFF circuitry and enables partial power-down when pulled to 0 V

Key Features

Feature	Design Value
Ultra-low static power	ICC ≤ 1.4 μA over full temperature range - extends battery life in coin-cell-powered wearables by years
IOFF partial power-down	Active output disable at VCC = 0 V with <0.75 μA leakage - enables safe hot-plug operation in modular systems
Schmitt-trigger inputs	Hysteresis ≥ 0.5×VCC - eliminates contact bounce and EMI-induced glitches on mechanical switch interfaces
Wide VCC compatibility	0.8 V to 3.6 V operation - interoperable with legacy 1.2 V ASICs, modern 0.8 V FPGAs, and 3.3 V microcontrollers
High-noise immunity	Input noise rejection >50% of VCC swing - sustains reliable operation in electrically noisy motor-drive or power-converter environments

Applications

Industrial Sensor Interface

Portable Medical Device

Use Scenario: Isolating and cleaning analog-to-digital converter (ADC) control signals in a battery-powered temperature logger with mechanical pushbuttons and long PCB traces.

IC Role / Device Role / Timing Role: Triple buffer provides noise-immune GPIO debouncing and level translation between 1.8 V MCU and 3.3 V ADC, with Schmitt inputs rejecting EMI from nearby switching regulators.

Use Value: Eliminates external RC filters and discrete transistors, reducing BOM count by 4 components while maintaining <100 ns timing margin at 1 MHz sampling rate.

Use Scenario: Signal conditioning for LED backlight dimming and tactile feedback drivers in a handheld pulse oximeter operating from a single CR2032 cell.

IC Role / Device Role / Timing Role: Buffers PWM enable lines and status flags between ultra-low-power 0.9 V SoC and 3.0 V display driver ICs, leveraging IOFF to prevent current leakage during sleep mode.

Use Value: Reduces standby current by 2.1 μA versus standard buffer alternatives, extending device runtime from 14 to 18 months on one battery.

Automotive Body Control Module

IoT Edge Node Gateway

Use Scenario: Interfacing door-lock actuator status sensors (open/closed) to a 3.3 V microcontroller in a 12 V vehicle electrical system with high conducted noise.

IC Role / Device Role / Timing Role: Acts as robust input conditioner for dry-contact switches exposed to load-dump transients; Schmitt inputs reject >200 mV burst noise without false triggering.

Use Value: Achieves ASIL-B compatible signal integrity without additional TVS diodes or ferrite beads, cutting board area by 12 mm².

Use Scenario: Level-shifting and buffering I²C clock/data lines between a 1.1 V BLE SoC and 1.8 V environmental sensor array in a wireless air-quality monitor.

IC Role / Device Role / Timing Role: Provides bidirectional signal integrity across mixed-voltage domains while maintaining I²C timing compliance (tpd ≤ 5.5 ns at 100 kHz).

Use Value: Enables direct connection without external MOSFET translators, reducing layout complexity and eliminating bus contention risk during power sequencing.

Equivalent & Alternatives

The following parts are listed as comparable options for similar triple buffer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC3G16DCUR	Higher ICC (max 10 μA), no Schmitt inputs, 1.65–5.5 V VCC range	Lacks noise immunity for slow-switching sensors; requires external filtering in noisy environments	Select only if higher VCC tolerance (>3.6 V) is required and input edge rates exceed 200 ns/V
74LVC1G16GW	Single-channel, same VCC range and Schmitt inputs, SOT353-5 package	Requires three separate packages to match triple functionality; increases PCB area and assembly cost	Choose only when board space allows discrete placement and thermal isolation of each buffer is preferred

Compared with SN74LVC3G16DCUR, the 74AUP3G16GMH offers 7× lower static current and intrinsic noise rejection-critical for energy harvesting nodes. Versus 74LVC1G16GW, it delivers identical performance in 1/3 the footprint and eliminates inter-channel skew in synchronized signal paths.

Availability

74AUP3G16GMH is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, automotive body control modules, and IoT edge node gateways requiring stable component supply across extended temperature ranges and ultra-low quiescent power.

Supply support for 74AUP3G16GMH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications where sub-microwatt static power, wide VCC flexibility, and robust noise immunity are mandatory design requirements.

FAQ

Does 74AUP3G16GMH support true bidirectional signal flow?

No. It is a unidirectional triple non-inverting buffer: inputs (1A/2A/3A) accept signals and outputs (1Y/2Y/3Y) drive loads. Each channel operates independently but lacks direction-control pins or bus-switch functionality. For bidirectional applications like I²C, external design techniques or dedicated bus buffers are required.

Can 74AUP3G16GMH be used with VCC = 0 V while inputs remain at 3.3 V?

Yes. The IOFF circuit ensures outputs are high-impedance and leakage remains ≤ ±0.75 μA even when VCC = 0 V and inputs/outputs are biased up to 3.6 V. This meets JESD78B Class II latch-up immunity and enables safe partial power-down in modular systems with shared signal buses.

What is the maximum capacitive load each output can drive while maintaining specified tpd?

Per Table 8, propagation delay is characterized up to CL = 30 pF across all VCC and temperature ranges. At VCC = 3.3 V and TA = +125 °C, tpd remains within 1.6–7.2 ns up to 30 pF. Driving >30 pF will increase delay nonlinearly and may violate setup/hold timing in high-speed interfaces.

Is the 74AUP3G16GMH pin-compatible with older 74AUP3G16 variants in VSSOP8?

Yes. The 74AUP3G16GMH shares identical SOT765-1 (VSSOP8) pinout, marking location ('5A'), and functional behavior with all prior 74AUP3G16DC/GF/GM variants. Revision 5 removes obsolete packages but preserves full electrical and mechanical compatibility for drop-in replacement in existing designs.

74AUP3G16GMH Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74AUP

Package/Case:: 8-XFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Logic Type:: Buffer, Non-Inverting

Number of Elements:: 3

Number of Bits per Element:: 1

Input Type:: -

Output Type:: Push-Pull

Current - Output High, Low:: 4mA, 4mA

Voltage - Supply:: 0.8V ~ 3.6V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-XQFN (1.6x1.6)

74AUP3G16GMH FAQ

1.How can I place an order for 74AUP3G16GMH through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP3G16GMH on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP3G16GMH reliable?

The price and inventory of 74AUP3G16GMH are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP3G16GMH is usually 5 days.

3.What payment methods are accepted for 74AUP3G16GMH?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP3G16GMH transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74AUP3G16GMH?

74AUP3G16GMH orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP3G16GMH order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP3G16GMH?

For technical support, including 74AUP3G16GMH datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP3G16GMH requirements.

6.How does Aetrix verify that 74AUP3G16GMH is sourced from the original manufacturer or authorized distributors?

All 74AUP3G16GMH products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP3G16GMH meets industry standards.

7.What is the process for return or replacement of 74AUP3G16GMH?

All 74AUP3G16GMH units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP3G16GMH, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP3G16GMH part is unused and in its original packaging.

Return procedure for 74AUP3G16GMH:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…