Nexperia USA Inc. 74AUP3G17GNX
- Part No.:
- 74AUP3G17GNX
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-XFDFN
- Datasheet:
-
74AUP3G17GNX.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 8XSON
- Quantity:
- Payment:

- Shipping:

Inventory:2,259
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Product details
Overview
74AUP3G17GNX from Nexperia is a low-power triple Schmitt trigger buffer IC designed for signal conditioning in ultra-low-voltage digital systems. It provides three independent hysteresis-enabled buffers operating from 0.8 V to 3.6 V, delivering jitter-free output transitions with input hysteresis voltage (VH) up to 1.31 V at 3.0 V VCC, ICC ≤ 0.9 μA max, and propagation delay as low as 1.5 ns at 3.0 V with 5 pF load - used in I²C bus level-shifting, sensor interface debouncing, and battery-powered microcontroller wake-up signal conditioning.
For engineers reviewing the 74AUP3G17GNX datasheet, 74AUP3G17GNX pinout, 74AUP3G17GNX application, or 74AUP3G17GNX equivalent, key selection criteria include its IOFF-enabled partial power-down capability, guaranteed operation down to 0.8 V, ±0.75 μA max input leakage across -40 °C to +125 °C, and XSON8 (SOT1116) 1.2 × 1.0 × 0.35 mm package with 8 terminals.
Technical Context
This device implements three independent Schmitt-trigger input stages feeding standard CMOS output buffers, each with asymmetric switching thresholds (VT+ and VT−) to reject noise on slow-rising/falling signals. Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current during partial power-down sequences in mixed-supply systems.
Dynamic performance is characterized by supply-voltage-dependent propagation delay (1.5–19.0 ns over 0.8–3.6 V), hysteresis voltage (0.07–1.31 V), and low dynamic power dissipation via CPD = 4.0 pF at 3.0 V - enabling use in high-density, thermally constrained PCB layouts without thermal derating concerns.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interfacing with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters |
| Max Supply Current (ICC) | 0.9 μA at 25 °C - enables multi-year battery life in always-on sensor nodes |
| Hysteresis Voltage (VH) | Up to 1.31 V at VCC = 3.0 V - rejects >1.3 V peak-to-peak noise on input signals |
| Propagation Delay (tpd) | 1.5 ns min at VCC = 3.0 V, CL = 5 pF - meets timing budgets for sub-500 MHz clock/data recovery paths |
| IOFF Leakage Current | ±0.75 μA max at VCC = 0 V - prevents cross-talk and power rail contamination in hot-plug or sleep-mode subsystems |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood automotive modules and industrial motor control enclosures |
| ESD Protection | HBM >5000 V, CDM >1000 V - survives handling and board-level ESD events without shielding |
Pinout & Package
XSON8 package (SOT1116): extremely thin small outline, no leads, 8-terminal surface-mount with 1.2 mm × 1.0 mm × 0.35 mm body height and pin 1 indicator in lower-left corner below marking code "pV".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A, 2A, 3A | Data Input | Three independent Schmitt-trigger inputs accepting 0–3.6 V signals regardless of VCC level |
| 1Y, 2Y, 3Y | Data Output | CMOS-compatible buffered outputs with rail-to-rail swing and IOFF disable when VCC = 0 V |
| VCC | Supply Voltage | Single supply pin supporting 0.8–3.6 V; powers all three channels and internal hysteresis circuitry |
| GND | Ground Reference | Common return path for supply and I/O; must be low-impedance to maintain noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Wide-Voltage Schmitt Trigger | Operates from 0.8 V to 3.6 V with VT+ and VT− thresholds scaling linearly with VCC - eliminates need for external bias networks |
| IOFF Partial Power-Down | Outputs go high-impedance when VCC = 0 V, preventing backfeed into powered sections - critical for FPGA I/O bank isolation |
| Ultra-Low Static Power | ICC ≤ 0.9 μA max across full temperature range - reduces quiescent load on coin-cell or energy-harvesting supplies |
| High Noise Immunity | Input hysteresis ≥0.5 V typical at 1.8 V VCC - suppresses false triggering from EMI-coupled transients on long PCB traces |
| Small Footprint | SOT1116 package (1.2 × 1.0 mm) saves >60% board area vs. SOIC-8 - enables dense wearable and IoT module designs |
Applications
| Industrial Sensor Interface | I²C Bus Level Translation |
|---|---|
Use Scenario: Debouncing mechanical switch inputs and cleaning noisy analog sensor outputs (e.g., thermistor, potentiometer) before ADC sampling in PLC I/O modules. IC Role / Device Role / Timing Role: Signal conditioner that converts slow, noisy analog-derived logic edges into clean, monotonic CMOS transitions synchronized to system clock domain. Use Value: Eliminates software debounce routines and external RC filters, reducing firmware complexity and BOM count while guaranteeing <100 ns jitter on wake-up interrupts. |
Use Scenario: Translating 1.8 V microcontroller I²C signals to 3.3 V peripheral side in battery-powered asset trackers with mixed-voltage peripherals. IC Role / Device Role / Timing Role: Bidirectional voltage translator leveraging Schmitt-trigger hysteresis to tolerate slow-rising open-drain bus edges and prevent metastability. Use Value: Enables reliable I²C communication across voltage domains without pull-up resistor recalculations or timing margin loss - maintains 400 kHz standard-mode timing compliance. |
| Low-Power Microcontroller Wake-Up | USB-C CC Line Signal Conditioning |
Use Scenario: Detecting button presses or external interrupt events in deep-sleep mode for wearables and smart tags where MCU VDD drops to 0.9 V. IC Role / Device Role / Timing Role: Always-on buffer with sub-1 μA ICC that asserts clean HIGH pulse to MCU's wake pin upon threshold-crossing event. Use Value: Extends battery life by >30% versus using MCU GPIOs directly, while ensuring deterministic wake latency (<200 ns) independent of supply droop. |
Use Scenario: Cleaning slow-rising USB-C Configuration Channel (CC) line signals before routing to USB PD controller in portable chargers and docks. IC Role / Device Role / Timing Role: Input conditioner that removes slew-rate-induced ambiguity during plug insertion/removal sequences. Use Value: Prevents false PD contract negotiation failures caused by marginal CC voltage transitions - improves plug/unplug reliability to >99.99%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Schmitt trigger buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G17DBVR | Wider VCC range (1.65–5.5 V); higher ICC (10 μA typ); no IOFF; larger SOT-23-5 package | Not suitable for sub-1.2 V systems or partial power-down architectures | Select only if operating above 1.65 V and IOFF is unnecessary |
| 74LVC3G17GM126 | Same 0.8–3.6 V range but uses XQFN12 package (2.5 × 1.0 mm); higher CPD (6.5 pF); no IOFF | Larger footprint and no power-down isolation limits use in space-constrained hot-swap modules | Prefer only when needing extra thermal margin or additional decoupling pad area |
Compared with SN74LVC1G17DBVR and 74LVC3G17GM126, the 74AUP3G17GNX uniquely combines sub-1 μA static current, IOFF protection, and 1.2 mm × 1.0 mm footprint - making it the sole choice for ultra-low-power, mixed-rail, space-constrained Schmitt buffering.
Availability
74AUP3G17GNX is available at Aetrix Electronics and suitable for industrial sensor interfaces, battery-powered IoT endpoints, USB-C accessory detection circuits, and automotive body-control module wake-up signal conditioning requiring stable component supply across extended temperature ranges.
Supply support for 74AUP3G17GNX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and mobile markets.
The 74AUP (Advanced Ultra-low Power) product line delivers sub-μA logic ICs optimized for energy harvesting, wearables, and always-on edge sensing - prioritizing supply voltage scalability and power-state integrity over raw speed.
FAQ
Does 74AUP3G17GNX support true bidirectional signal translation?
No - it is a unidirectional Schmitt trigger buffer with separate input (A) and output (Y) pins. While it can condition signals on open-drain buses like I²C when used with external pull-ups, it lacks internal pass-gate architecture or automatic direction sensing required for true bidirectional level translation.
What is the minimum recommended load capacitance for stable operation?
The device is characterized down to 5 pF load capacitance per output, and no minimum load is specified. Operation remains stable with capacitive loads from 0 pF to 30 pF; however, propagation delay increases linearly with CL - e.g., tpd rises from 1.5 ns (5 pF) to 3.1 ns (30 pF) at VCC = 3.0 V.
Can the 74AUP3G17GNX be used with VCC = 0 V while inputs are driven at 3.3 V?
Yes - the inputs are overvoltage tolerant up to 3.6 V regardless of VCC state. With VCC = 0 V, the IOFF circuit disables outputs, and input leakage remains ≤±0.75 μA, satisfying JESD78 Class II latch-up immunity and preventing damage or unintended current paths.
How does hysteresis voltage (VH) scale with supply voltage?
VH scales approximately linearly with VCC: 0.07 V at 0.8 V, 0.46 V at 1.1 V, 0.56 V at 1.4 V, 0.66 V at 1.65 V, 0.92 V at 2.3 V, and 1.31 V at 3.0 V. This ensures consistent noise margin percentage (≈30–45% of VCC) across the full operating range.
74AUP3G17GNX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 3
- Number of Bits per Element:
- 1
- Input Type:
- Schmitt Trigger
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON, SOT833-1 (1.95x1)
74AUP3G17GNX FAQ
1.How can I place an order for 74AUP3G17GNX through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP3G17GNX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP3G17GNX reliable?
The price and inventory of 74AUP3G17GNX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP3G17GNX is usually 5 days.
3.What payment methods are accepted for 74AUP3G17GNX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP3G17GNX transactions.
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4.How is shipping managed for 74AUP3G17GNX?
74AUP3G17GNX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP3G17GNX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP3G17GNX?
For technical support, including 74AUP3G17GNX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP3G17GNX requirements.
6.How does Aetrix verify that 74AUP3G17GNX is sourced from the original manufacturer or authorized distributors?
All 74AUP3G17GNX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP3G17GNX meets industry standards.
7.What is the process for return or replacement of 74AUP3G17GNX?
All 74AUP3G17GNX units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP3G17GNX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP3G17GNX part is unused and in its original packaging.
Return procedure for 74AUP3G17GNX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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