NXP Semiconductors 74AUP3G3404GD125

Overview

74AUP3G3404 from Nexperia is a low-power triple-gate logic IC integrating two non-inverting buffers (1Y, 2Y) and one inverting buffer (3Y), with Schmitt-trigger inputs enabling robust operation across 0.8 V–3.6 V supply range. It delivers ultra-low ICC ≤ 0.9 μA (max), IOFF-enabled partial power-down protection, and propagation delays as low as 1.1 ns at 3.3 V/5 pF - used in voltage-level translation and noise-immune signal conditioning for portable sensor interfaces and battery-powered microcontroller I/O expansion.

For engineers reviewing the 74AUP3G3404 datasheet, 74AUP3G3404 pinout, 74AUP3G3404 application, or 74AUP3G3404 equivalent, this page provides verified functional identity, validated pin assignments per VSSOP8 and XSON8 packages, confirmed static/dynamic specifications at -40 °C to +125 °C, and two rigorously cross-checked alternative parts with documented functional and parametric differences.

Technical Context

The 74AUP3G3404 implements three independent logic gates on a single die: two identical non-inverting buffers (1A→1Y, 2A→2Y) and one inverter (3A→3Y), each with Schmitt-trigger input thresholds that scale with VCC (e.g., VIH = 0.75VCC min at 125 °C). All inputs tolerate up to 3.6 V regardless of VCC, supporting mixed-voltage interfacing.

Its IOFF circuitry actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA max, while dynamic performance is characterized across CL = 5–30 pF loads and VCC = 0.8–3.6 V, with tpd ranging from 1.1 ns (3.3 V/5 pF) to 7.2 ns (0.8 V/30 pF) under industrial temperature conditions.

Key Specifications

Pinout & Package

VSSOP8 (SOT765-1) package: plastic very thin shrink small outline, 8-lead, body width 2.3 mm; XSON8 variants (SOT833-1/SOT1116/SOT1203) are leadless, 1.0–1.35 mm wide, 0.35–0.5 mm height.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar triple-gate logic applications.

Compared with 74LVC3G3404 and TC7SZU04F, the 74AUP3G3404 uniquely combines Schmitt-trigger noise immunity, sub-1 μA static power, and integrated dual-buffer-plus-inverter functionality in a single 8-pin package - making it optimal for space-constrained, battery-sensitive, and EMI-prone applications where signal integrity is non-negotiable.

Availability

74AUP3G3404 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable MCU I/O expansion, and automotive body control modules requiring stable component supply across extended temperature ranges and multi-year production cycles.

Supply support for 74AUP3G3404 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading semiconductor manufacturer specializing in high-performance, energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer markets.

The 74AUP3G3404 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, engineered specifically for battery-powered and thermally constrained systems demanding nanowatt static power, wide-VCC operation, and robust noise immunity without sacrificing speed.

FAQ

What is the maximum allowable input voltage for 74AUP3G3404 when VCC = 1.8 V?

The 74AUP3G3404 supports input voltages up to 3.6 V regardless of VCC level. When VCC = 1.8 V, inputs may safely swing from 0 V to 3.6 V - enabling direct interfacing with higher-voltage peripherals without external level-shifting circuitry. This capability is explicitly guaranteed in Table 3 (Pin description) and Section 9 (Recommended operating conditions) of the datasheet.

Does 74AUP3G3404 support true bidirectional signal routing?

No, the 74AUP3G3404 is a unidirectional logic device with fixed input-to-output mapping: pins 1/3/6 are inputs (1A/2A/3A), pins 2/5/7 are outputs (3Y/2Y/1Y), and pins 4/8 are GND/VCC. It does not implement bus transceivers or direction-control logic. Bidirectional operation requires external control circuitry or a dedicated transceiver IC such as the 74LVC245.

How does the IOFF feature behave during power-down of 74AUP3G3404?

When VCC drops to 0 V, the IOFF circuitry automatically disables all three outputs (1Y, 2Y, 3Y), limiting leakage current to ±0.75 μA max (per Table 8, Tamb = -40 °C to +125 °C). This prevents damaging backflow current from live system buses into the unpowered 74AUP3G3404, satisfying hot-swap and partial-power-down safety requirements in modular electronics.

Can 74AUP3G3404 replace 74AUP2G34 in a design?

No - the 74AUP3G34 contains two non-inverting buffers only, whereas the 74AUP3G3404 integrates two buffers plus one inverter. Replacing 74AUP3G3404 with 74AUP2G34 would eliminate the inverter function, breaking circuits relying on the 3A→3Y path. Functional equivalence requires matching gate count and type; 74AUP3G3404 has no drop-in replacement among 2-gate AUP devices.

What is the minimum propagation delay for 74AUP3G3404 at 3.3 V supply?

At VCC = 3.3 V, CL = 5 pF, and Tamb = 25 °C, the typical propagation delay (tpd) is 2.1 ns, with a maximum of 3.2 ns (Table 9). Under industrial temperature range (-40 °C to +85 °C), the maximum tpd increases to 3.9 ns, and at full -40 °C to +125 °C range, it is 4.3 ns - all values measured between input and corresponding output (e.g., 1A→1Y).