Nexperia USA Inc. 74AUP3G3404GDH

Overview

74AUP3G3404GDH from Nexperia is a low-power triple-gate logic device integrating two non-inverting buffers (1Y, 2Y) and one inverting buffer (3Y), with Schmitt-trigger inputs enabling robust noise immunity across 0.8 V–3.6 V supply operation. It features IOFF partial power-down protection, <0.9 μA max ICC at 25 °C, and operates from –40 °C to +125 °C - deployed in battery-powered sensor interfaces and level-shifting I/O expansion circuits.

For engineers reviewing the 74AUP3G3404GDH datasheet, 74AUP3G3404GDH pinout, 74AUP3G3404GDH application, or 74AUP3G3404GDH equivalent, this page delivers verified functional identity, validated pin mapping for SOT765-1 (VSSOP8), confirmed Schmitt-trigger input thresholds, IOFF leakage specs, and real-world use context for ultra-low-power digital signal conditioning.

Technical Context

This device implements three independent logic gates on a single die: two A→Y non-inverting paths and one A→Y inverting path, each with hysteresis-enabled Schmitt-trigger inputs. Input thresholds scale with VCC (e.g., VIH = 0.65VCC min at 1.4 V), ensuring reliable switching under slow-rising signals and noisy environments.

The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA max over –40 °C to +125 °C. Propagation delay ranges from 1.1 ns (VCC = 3.3 V, CL = 5 pF) to 33.6 ns (VCC = 0.8 V, CL = 30 pF), supporting both high-speed and ultra-low-voltage operation.

Key Specifications

Pinout & Package

VSSOP8 package (SOT765-1): plastic very thin shrink small outline, 8 leads, body width 2.3 mm, 0.5 mm pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar triple-gate logic applications.

Compared with 74LVC3G3404 and TC7WZU04F, the 74AUP3G3404GDH uniquely combines sub-μA static power, Schmitt-trigger noise immunity, and IOFF protection - making it the sole option for battery-critical, multi-voltage, and hot-swap-sensitive designs.

Availability

74AUP3G3404GDH is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power MCU GPIO expansion, and automotive body control modules requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP3G3404GDH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions with focus on efficiency, reliability, and miniaturization for consumer, industrial, and automotive markets.

The 74AUP (Advanced Ultra Low Power) product line targets ultra-low-power digital signal conditioning in space-constrained, battery-operated, and multi-rail embedded systems - emphasizing sub-μA static current and robust noise immunity.

FAQ

Does 74AUP3G3404GDH support mixed-voltage I/O when VCC = 1.8 V?

Yes - all inputs accept voltages up to 3.6 V regardless of VCC, enabling direct connection to 3.3 V sensors or communication lines while operating from a 1.8 V rail. Output levels remain compatible with 1.8 V logic families, with VOH ≥ 1.6 V and VOL ≤ 0.31 V at IO = ±1.9 mA.

Can the Schmitt-trigger inputs be disabled to use standard CMOS thresholds?

No - Schmitt-trigger behavior is inherent to the input structure and cannot be disabled. The hysteresis is fixed per VCC (e.g., ~120 mV at 1.2 V), providing consistent noise margin but preventing precise threshold tuning. This is intentional for robustness in noisy environments.

What is the maximum capacitive load the outputs can drive reliably?

The outputs are characterized up to 30 pF load capacitance, with propagation delay increasing predictably (e.g., 2.9 ns to 7.2 ns at VCC = 3.3 V). For loads >30 pF, rise/fall times degrade and VOH/VOL margins shrink; external buffering is recommended beyond 50 pF to maintain timing integrity.

Is thermal derating required for continuous operation at +125 °C ambient?

Yes - for the SOT765-1 (VSSOP8) package, total power dissipation derates linearly at 4.9 mW/K above +99 °C. At +125 °C ambient, Ptot must be limited to ≤127 mW (250 mW − 4.9 × 26) to stay within safe junction temperature limits, assuming typical 0.9 μA ICC and negligible dynamic load.