Nexperia USA Inc. 74AUP3G3404GTX

Overview

74AUP3G3404 from Nexperia is a low-power triple-gate logic device integrating two non-inverting buffers (1Y, 2Y) and one inverting buffer (3Y), with Schmitt-trigger inputs enabling robust noise immunity across 0.8 V–3.6 V supply operation. It delivers ICC ≤ 1.4 μA max at −40 °C to +125 °C, supports IOFF partial power-down mode, and operates in industrial and automotive-qualified temperature ranges. This device is used in voltage-level translation, signal conditioning, and noise-prone sensor interface circuits.

For engineers reviewing the 74AUP3G3404 datasheet, 74AUP3G3404 pinout, 74AUP3G3404 application, or 74AUP3G3404 equivalent, key selection criteria include its dual-buffer + single-inverter topology, sub-1.5 μA static current, Schmitt-trigger input hysteresis, IOFF-enabled power sequencing, and compatibility with 0.8 V–3.6 V mixed-voltage systems.

Technical Context

The 74AUP3G3404 implements three independent logic gates on a single die: two identical non-inverting buffers (1A→1Y, 2A→2Y) and one inverting buffer (3A→3Y), each with Schmitt-trigger inputs ensuring ≥100 mV hysteresis across all VCC. Input thresholds scale with supply voltage (e.g., VIH = 0.70×VCC min at 0.8 V), supporting reliable operation in noisy, slow-rising environments.

Its IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA max, enabling safe hot-insertion and multi-rail power sequencing. Dynamic performance is load-dependent: tPD = 1.1–4.3 ns (CL = 5–30 pF, VCC = 3.0–3.6 V), with CPD = 4.0 pF enabling precise dynamic power estimation (PD = CPD × VCC² × fi × N).

Key Specifications

Pinout & Package

74AUP3G3404 is available in four leadless or fine-pitch packages: VSSOP8 (SOT765-1), XSON8 (SOT833-1), XSON8 (SOT1116), and XSON8 (SOT1203). All variants are 8-terminal, surface-mount devices with identical pin function mapping and pin 1 index located below the marking code.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar triple-gate logic applications.

Compared with 74AUP3G14 and SN74LVC3G34, the 74AUP3G3404 uniquely combines dual buffering and single inversion with Schmitt inputs and IOFF - making it the only option for mixed-polarity, noise-immune, multi-rail sequenced designs in space-constrained applications.

Availability

74AUP3G3404 is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power MCU I/O expansion, automotive body control modules, and USB-C power delivery sequencing requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP3G3404 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP (Advanced Ultra-low Power) product line targets battery-sensitive and thermally constrained applications, emphasizing sub-μA static current, wide VCC scalability, and robust IOFF behavior for modern mixed-voltage embedded systems.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The absolute maximum input voltage is −0.5 V to +4.6 V regardless of VCC state. When VCC = 0 V, the IOFF circuit limits input-to-output leakage to ±0.75 μA max, allowing inputs to be driven up to 3.6 V safely without back-current damage - critical for hot-swap and multi-rail isolation.

Does the 74AUP3G3404 support 0.8 V logic levels with guaranteed timing?

Yes. At VCC = 0.8 V, tPD is specified up to 16.0 ns (CL = 5 pF) with VIH ≥ 0.70×VCC and VIL ≤ 0.30×VCC. Propagation delay remains monotonic and fully characterized down to 0.8 V, enabling interoperability with sub-1.0 V processors and ultra-low-power sensor nodes.

How does the Schmitt-trigger hysteresis vary with supply voltage?

Hysteresis is internally scaled and maintains ≥100 mV across 0.8 V–3.6 V. For example, at VCC = 1.2 V, VIH ≈ 0.78 V and VIL ≈ 0.36 V (Δ ≈ 420 mV); at VCC = 3.3 V, VIH ≈ 2.0 V and VIL ≈ 0.9 V (Δ ≈ 1.1 V). This ensures consistent noise margin regardless of rail voltage.

Can the 74AUP3G3404 replace a discrete 74AUP1G04 + 74AUP1G34 pair?

Yes - it integrates one inverter (3A→3Y) and two buffers (1A→1Y, 2A→2Y) in a single 8-pin package. Pin-compatible replacement reduces PCB area by ~40% versus two SOT353 devices and eliminates inter-device skew, though layout must accommodate shared VCC/GND and verify thermal derating per package variant.