NXP Semiconductors 74AUP3G34GDH
- Part No.:
- 74AUP3G34GDH
- Manufacturer:
- NXP Semiconductors
- Package:
- -
- Datasheet:
-
74AUP3G34GDH.pdf
- Description:
- NEXPERIA 74AUP3G34 - NON INVERTI
- Quantity:
- Payment:

- Shipping:

Inventory:2,928
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AUP3G34GDH from Nexperia is a low-power triple buffer IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply range, delivering ultra-low static current (≤0.9 μA max), IOFF-enabled partial power-down protection, and propagation delay as low as 1.4 ns at 3.6 V/5 pF - deployed in battery-powered sensor interfaces and portable logic level translation.
For engineers reviewing the 74AUP3G34GDH datasheet, 74AUP3G34GDH pinout, 74AUP3G34GDH application, or 74AUP3G34GDH equivalent, key selection criteria include its 0.8–3.6 V wide-VCC tolerance, guaranteed operation up to +125 °C, Schmitt-trigger noise immunity, IOFF backflow prevention, and compatibility with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains.
Technical Context
This device implements three independent non-inverting buffers, each with Schmitt-trigger input thresholds that tolerate slow-rising/falling signals and suppress noise-induced glitches. The IOFF circuit actively disables outputs when VCC = 0 V, blocking damaging back-current during partial power-down sequences in multi-rail systems.
All inputs accept voltages up to 3.6 V regardless of VCC level, enabling mixed-voltage interfacing. Static power consumption remains ≤0.9 μA over full temperature range (−40 °C to +125 °C) and entire supply range, supporting always-on subsystems in wearables and IoT edge nodes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic families without level shifters. |
| Max ICC (Static) | 0.9 μA at −40 °C to +125 °C - enables multi-year battery life in ultra-low-power sensor nodes and wake-up circuits. |
| Propagation Delay | 1.4 ns typical at VCC = 3.0 V, CL = 5 pF - ensures timing-critical signal buffering in high-speed control loops and clock distribution paths. |
| IOFF Leakage | ±0.75 μA max at VCC = 0 V - prevents destructive back-current flow when upstream logic is powered while this device is off. |
| Input Thresholds | VIL ≤ 0.3×VCC, VIH ≥ 0.65×VCC (at +125 °C) - provides robust noise margin against rail-to-rail crosstalk in dense PCB layouts. |
| ESD Rating | HBM >5000 V, CDM >1000 V - meets industrial IEC 61000-4-2 system-level ESD requirements without external protection. |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive modules, industrial motor drives, and outdoor telecom equipment. |
Pinout & Package
XSON8 package (SOT833-1): plastic extremely thin small outline, no leads, 8-terminal, 1.0 mm × 1.95 mm × 0.5 mm body, thermal pad omitted, pin 1 marked by notch or dot in lower-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A, 2A, 3A | Independent data inputs | Three separate logic inputs accepting 0–3.6 V; each drives one output with Schmitt-trigger hysteresis. |
| 1Y, 2Y, 3Y | Independent buffered outputs | Non-inverting, rail-to-rail CMOS outputs; each capable of sourcing/sinking ±4 mA at 3.0 V. |
| GND | Ground reference | Primary return path for all internal logic and I/O; must be low-impedance to minimize ground bounce. |
| VCC | Power supply | Single supply input; powers all three buffers and IOFF circuitry; decoupling capacitor required within 1 cm. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 0.8 V to 3.6 V enables direct integration into heterogeneous voltage domains without external regulators. |
| Schmitt-trigger inputs | Input hysteresis ≥0.1×VCC improves noise rejection on long traces or noisy PCB environments. |
| IOFF partial power-down | Outputs go high-impedance when VCC = 0 V, preventing backfeed in hot-swap or sequenced power systems. |
| Low dynamic power | CPD = 4.0 pF at 3.6 V - minimizes switching power in high-frequency enable/disable cycles. |
| High ESD robustness | HBM >5 kV and CDM >1 kV reduce need for external TVS diodes in handheld and field-deployable gear. |
Applications
| Industrial Sensor Interface | Wearable Health Monitor |
|---|---|
|
Use Scenario: Buffering analog sensor outputs digitized by low-voltage ADCs in factory-floor vibration sensors. IC Role / Device Role / Timing Role: Signal conditioning buffer isolating noisy analog front-end from digital domain; preserves edge integrity during 100 kHz sampling. Use Value: Schmitt-trigger inputs reject EMI-induced jitter on 10 cm PCB traces; 0.9 μA ICC extends battery life beyond 5 years in maintenance-free deployments. |
Use Scenario: Level-shifting ECG electrode signals between 1.2 V analog front-end and 3.3 V Bluetooth SoC in chest-worn patch. IC Role / Device Role / Timing Role: Voltage-tolerant non-inverting buffer enabling bidirectional logic compatibility without active translators. Use Value: 0.8 V minimum VCC allows operation directly from single-cell Li-ion (2.7–4.2 V) via LDO dropout; IOFF prevents leakage during sleep mode. |
| Automotive Body Control Module | Smart Home Hub Gateway |
|
Use Scenario: Interfacing 5 V legacy CAN transceiver status pins to 1.8 V microcontroller GPIO in door module ECUs. IC Role / Device Role / Timing Role: Input-tolerant buffer translating 5 V open-drain signals to 1.8 V CMOS levels with glitch-free response. Use Value: Inputs rated to 3.6 V withstand transient overshoots on shared harnesses; −40 °C to +125 °C rating meets AEC-Q100 Grade 2. |
Use Scenario: Isolating Zigbee radio reset line from 3.3 V host MCU to prevent latch-up during firmware updates. IC Role / Device Role / Timing Role: Controlled-enable buffer ensuring clean reset assertion with defined rise/fall times and no floating states. Use Value: Propagation delay <2 ns eliminates timing skew in sub-microsecond reset windows; low ICC reduces standby power in always-listening mode. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC3G34DCUR | Higher ICC (max 10 μA), no IOFF, VCC min = 1.65 V | Not suitable for sub-1.65 V systems or partial power-down designs | Select only if operating exclusively ≥1.65 V and IOFF is unnecessary. |
| 74LVC3G17GW,125 | Schmitt-trigger outputs (not inputs), higher propagation delay (≥3.5 ns), no IOFF | Limited noise immunity on input side; unsuitable for slow-rising sensor signals | Prefer only when output hysteresis is required and input slew rate is controlled. |
Compared with SN74LVC3G34DCUR and 74LVC3G17GW,125, the 74AUP3G34GDH uniquely combines sub-1 V operation, IOFF protection, and Schmitt-trigger inputs - making it the sole choice for ultra-low-power, mixed-voltage, and hot-plug-resilient buffer applications.
Availability
74AUP3G34GDH is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable health monitors, automotive body control modules, and smart home hub gateways requiring stable component supply across extended temperature and voltage ranges.
Supply support for 74AUP3G34GDH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.
The 74AUP (Advanced Ultra-low Power) product line targets battery-constrained and thermally sensitive applications - designed specifically for ultra-low static/dynamic power, wide-VCC interoperability, and robust operation in harsh environments.
FAQ
Does 74AUP3G34GDH support true 0 V to VCC input voltage range?
Yes - inputs tolerate 0 V to 3.6 V regardless of VCC level (down to 0.8 V), enabling safe interfacing with higher-voltage peripherals like 5 V sensors or legacy microcontrollers without clamping diodes or resistive dividers.
What is the maximum capacitive load this device can drive reliably?
The device is characterized up to 30 pF load capacitance with propagation delay specified at 5 pF, 10 pF, 15 pF, and 30 pF. Driving >30 pF may increase tpd and reduce noise margin but does not damage the part; layout decoupling and trace impedance control are recommended above 20 pF.
Can 74AUP3G34GDH be used in hot-swap applications?
Yes - the IOFF circuit ensures outputs enter high-impedance state when VCC drops below ~0.2 V, preventing back-current flow from live signal lines into a powered-down device, satisfying hot-swap safety requirements in modular power architectures.
Is there a thermal pad on the SOT833-1 (XSON8) package of 74AUP3G34GDH?
No - the SOT833-1 package has no exposed thermal pad; thermal dissipation relies solely on soldered terminals and PCB copper area. For high-duty-cycle operation, use ≥25 mm² of 1-oz copper pour connected to GND and VCC pins to maintain junction temperature within −40 °C to +125 °C limits.
74AUP3G34GDH Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- *
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- -
- Number of Elements:
- -
- Number of Bits per Element:
- -
- Input Type:
- -
- Output Type:
- -
- Current - Output High, Low:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
74AUP3G34GDH FAQ
1.How can I place an order for 74AUP3G34GDH through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP3G34GDH on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP3G34GDH reliable?
The price and inventory of 74AUP3G34GDH are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP3G34GDH is usually 5 days.
3.What payment methods are accepted for 74AUP3G34GDH?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP3G34GDH transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP3G34GDH?
74AUP3G34GDH orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP3G34GDH order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP3G34GDH?
For technical support, including 74AUP3G34GDH datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP3G34GDH requirements.
6.How does Aetrix verify that 74AUP3G34GDH is sourced from the original manufacturer or authorized distributors?
All 74AUP3G34GDH products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP3G34GDH meets industry standards.
7.What is the process for return or replacement of 74AUP3G34GDH?
All 74AUP3G34GDH units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP3G34GDH, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP3G34GDH part is unused and in its original packaging.
Return procedure for 74AUP3G34GDH:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP3G34GDH Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

