Nexperia USA Inc. 74AXP1G00GN125

Overview

74AXP1G00GN125 from Nexperia is a single 2-input NAND gate with Schmitt-trigger inputs, designed for ultra-low-power logic interfacing in battery-powered and voltage-scalable systems. It operates across 0.7 V to 2.75 V supply range, delivers <3.2 ns propagation delay at 2.3–2.7 V, and features IOFF partial power-down protection. It is used in I²C bus level translation, sensor interface conditioning, and portable MCU peripheral control.

For engineers reviewing the 74AXP1G00GN125 datasheet, 74AXP1G00GN125 pinout, 74AXP1G00GN125 application, or 74AXP1G00GN125 equivalent, key selection criteria include its sub-1.0 V operation capability, 0.5 pF input capacitance, IOFF-enabled system power sequencing, and XSON6 (SOT1115) 0.9 × 1.0 mm package compatibility with high-density PCB layouts.

Technical Context

This device implements a single NAND logic function with hysteresis-equipped Schmitt-trigger inputs, enabling robust noise immunity against slow-rising signals in mixed-voltage domains. Its IOFF circuit actively disables output leakage when VCC = 0 V, supporting hot-insertion and partial power-down modes without backflow current.

It complies with JEDEC standards JESD8-12A.01 through JESD8-5A.01 across four voltage bands and meets HBM ESD >2 kV and CDM >1000 V requirements. Static ICC remains ≤0.6 μA at 85 °C, while dynamic CPD is 2.5 pF at 1.2 V - optimized for low-energy switching in always-on subsystems.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): extremely thin small outline, no leads, 6 terminals, body size 0.9 × 1.0 × 0.35 mm. Pin 1 indicator located at lower-left corner below marking code "rA".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NAND gate applications.

Compared with 74LVC1G00GV and SN74LVC1G00DBVR, the 74AXP1G00GN125 uniquely supports 0.7 V operation, integrates Schmitt-trigger inputs for noise resilience, and provides IOFF for safe multi-rail sequencing - making it the sole choice for energy-constrained, mixed-voltage, and high-noise industrial or portable designs.

Availability

74AXP1G00GN125 is available at Aetrix Electronics and suitable for USB-C interface design, I²C level translation, portable medical sensor conditioning, and industrial PLC input debouncing requiring stable component supply and long-term manufacturability.

Supply support for 74AXP1G00GN125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and mobile markets.

The 74AXP series targets ultra-low-power, voltage-scalable logic applications - specifically engineered for battery-operated devices, energy-harvesting systems, and multi-voltage SoC interconnects where static/dynamic power and IOFF safety are critical.

FAQ

Can 74AXP1G00GN125 operate reliably at 0.75 V supply?

Yes. The device is fully specified down to 0.7 V with guaranteed propagation delay (≤36 ns), input thresholds (VIH ≥ 0.75×VCC), and output drive (VOL ≤ 0.25×VCC) across −40 °C to +85 °C. At 0.75 V, typical tpd is 12 ns and ICC remains ≤0.3 μA - validated per Table 7 and Table 8 of the official datasheet.

What is the maximum capacitive load this NAND gate can drive while meeting timing specs?

At VCC = 2.5 V and Tamb = 25 °C, the device maintains tpd ≤3.0 ns with CL ≤15 pF (see Fig. 7). For CL = 30 pF, tpd increases to ~6 ns - still functional but outside guaranteed spec. Layout parasitics must be included; total load should stay ≤12 pF for margin in production designs.

Does pin 5 (n.c.) require any PCB treatment?

No. Pin 5 is internally unconnected and electrically isolated. It may be left floating, tied to GND, or routed as a keep-out zone - no electrical impact. However, grounding it improves thermal dissipation slightly and avoids potential antenna effects in RF-sensitive layouts.

How does IOFF behave when VCC is ramped down during system shutdown?

IOFF activates when VCC drops below ~0.2 V, forcing Y into high-impedance state within 100 ns. Output leakage remains ≤±0.1 μA even if A/B/Y are biased to 2.75 V - verified under "Power-off leakage current" (ΔIOFF) test conditions in Table 7. This prevents backfeed into powered-down domains during controlled power sequencing.